From nobody Fri Dec 19 14:08:10 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7629040BFE; Wed, 20 Dec 2023 15:27:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="cN+CV77e" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKAJMu1026336; Wed, 20 Dec 2023 16:27:35 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=sr+3zBBOyZ1rB6MCRzn+XuV35G6DJ6CNLI/Iw1vfcPM=; b=cN +CV77eviOSxn0bVgp2GyAfZ3TVFTs6prle75/tYBfNHClLEzOb5/zmiAcyKnFgeV FWxjSC8yo09ZJKJSBsyAtF4JNjWJ81ZtxyK0hC/UCLeo2qMGWERST7Vf3OdM6UJQ EbspeyD7wpAi9Wkj6ltOnJ3r31UrPfJpp4JHLMB7f4j65PaYFN2uFBiHw6wJUkhY CpoSnjhOd2qggBz/f2tixN/TCCxzeqQ4KrRtRp6e8R9HzG+n0hkkk8ktOYAhW0m+ tIH9h4aJVcUVy8/j8fuKsGf3Cog15XR7WaoRFrEcbPpB08YhoRpnPVS8fm+X3CY8 awO87sW9D6//1zkn/Q4g== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v126m2ppn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:27:35 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 47162100059; Wed, 20 Dec 2023 16:27:35 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3AF7721ED29; Wed, 20 Dec 2023 16:27:35 +0100 (CET) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 16:27:34 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v4 1/5] dt-bindings: media: Document STM32MP25 VDEC & VENC video codecs Date: Wed, 20 Dec 2023 16:27:28 +0100 Message-ID: <20231220152732.2138260-2-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> References: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_09,2023-12-20_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add STM32MP25 VDEC video decoder & VENC video encoder bindings. Signed-off-by: Hugues Fruchet --- .../media/st,stm32mp25-video-codec.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32mp25-vi= deo-codec.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-video-cod= ec.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.= yaml new file mode 100644 index 000000000000..e167e3b1bec3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder + +maintainers: + - Hugues Fruchet + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware + decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1) + and a VENC video hardware encoder peripheral based on Verisilicon + VC8000NanoE IP (former Hantro H1). + +properties: + compatible: + enum: + - st,stm32mp25-vdec + - st,stm32mp25-venc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + video-codec@580d0000 { + compatible =3D "st,stm32mp25-vdec"; + reg =3D <0x580d0000 0x3c8>; + interrupts =3D ; + clocks =3D <&ck_icn_p_vdec>; + }; --=20 2.25.1 From nobody Fri Dec 19 14:08:10 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BFA04655A; Wed, 20 Dec 2023 15:27:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="4evL+1CJ" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKAKjSV011909; Wed, 20 Dec 2023 16:27:36 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; 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Wed, 20 Dec 2023 16:27:35 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v4 2/5] media: hantro: add support for STM32MP25 VDEC Date: Wed, 20 Dec 2023 16:27:29 +0100 Message-ID: <20231220152732.2138260-3-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> References: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_09,2023-12-20_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add support for STM32MP25 VDEC video hardware decoder. Support of H264/VP8 decoding. No post-processor support. VDEC has its own reset/clock/irq. Signed-off-by: Hugues Fruchet Reviewed-by: Nicolas Dufresne --- drivers/media/platform/verisilicon/Kconfig | 14 ++- drivers/media/platform/verisilicon/Makefile | 3 + .../media/platform/verisilicon/hantro_drv.c | 3 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_vdec_hw.c | 92 +++++++++++++++++++ 5 files changed, 110 insertions(+), 3 deletions(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c diff --git a/drivers/media/platform/verisilicon/Kconfig b/drivers/media/pla= tform/verisilicon/Kconfig index e65b836b9d78..7642ff9cf96c 100644 --- a/drivers/media/platform/verisilicon/Kconfig +++ b/drivers/media/platform/verisilicon/Kconfig @@ -4,7 +4,7 @@ comment "Verisilicon media platform drivers" =20 config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPIL= E_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || ARCH_S= TM32 || COMPILE_TEST depends on V4L_MEM2MEM_DRIVERS depends on VIDEO_DEV select MEDIA_CONTROLLER @@ -16,8 +16,8 @@ config VIDEO_HANTRO select V4L2_VP9 help Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image - encoding and decoding. + Rockchip, NXP i.MX8M and STM32MP25 SoCs, which accelerate video + and image encoding and decoding. To compile this driver as a module, choose M here: the module will be called hantro-vpu. =20 @@ -52,3 +52,11 @@ config VIDEO_HANTRO_SUNXI default y help Enable support for H6 SoC. + +config VIDEO_HANTRO_STM32MP25 + bool "Hantro STM32MP25 support" + depends on VIDEO_HANTRO + depends on ARCH_STM32 || COMPILE_TEST + default y + help + Enable support for STM32MP25 SoCs. diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/pl= atform/verisilicon/Makefile index 6ad2ef885920..5854e0f0dd32 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -39,3 +39,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) +=3D \ =20 hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) +=3D \ sunxi_vpu_hw.o + +hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) +=3D \ + stm32mp25_vdec_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/medi= a/platform/verisilicon/hantro_drv.c index a9fa05ac56a9..2db27c333924 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -733,6 +733,9 @@ static const struct of_device_id of_hantro_match[] =3D { #endif #ifdef CONFIG_VIDEO_HANTRO_SUNXI { .compatible =3D "allwinner,sun50i-h6-vpu-g2", .data =3D &sunxi_vpu_vari= ant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_STM32MP25 + { .compatible =3D "st,stm32mp25-vdec", .data =3D &stm32mp25_vdec_variant,= }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media= /platform/verisilicon/hantro_hw.h index 7f33f7b07ce4..b7eccc1a96fc 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -406,6 +406,7 @@ extern const struct hantro_variant rk3568_vpu_variant; extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; +extern const struct hantro_variant stm32mp25_vdec_variant; =20 extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c b/drive= rs/media/platform/verisilicon/stm32mp25_vdec_hw.c new file mode 100644 index 000000000000..aa8b0f751390 --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 VDEC video decoder driver + * + * Copyright (C) STMicroelectronics SA 2022 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include "hantro.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_vdec_fmts[] =3D { + { + .fourcc =3D V4L2_PIX_FMT_NV12, + .codec_mode =3D HANTRO_MODE_NONE, + .frmsize =3D { + .min_width =3D FMT_MIN_WIDTH, + .max_width =3D FMT_FHD_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D FMT_MIN_HEIGHT, + .max_height =3D FMT_FHD_HEIGHT, + .step_height =3D MB_DIM, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_VP8_FRAME, + .codec_mode =3D HANTRO_MODE_VP8_DEC, + .max_depth =3D 2, + .frmsize =3D { + .min_width =3D FMT_MIN_WIDTH, + .max_width =3D FMT_FHD_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D FMT_MIN_HEIGHT, + .max_height =3D FMT_FHD_HEIGHT, + .step_height =3D MB_DIM, + }, + }, + { + .fourcc =3D V4L2_PIX_FMT_H264_SLICE, + .codec_mode =3D HANTRO_MODE_H264_DEC, + .max_depth =3D 2, + .frmsize =3D { + .min_width =3D FMT_MIN_WIDTH, + .max_width =3D FMT_FHD_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D FMT_MIN_HEIGHT, + .max_height =3D FMT_FHD_HEIGHT, + .step_height =3D MB_DIM, + }, + }, +}; + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] =3D { + [HANTRO_MODE_VP8_DEC] =3D { + .run =3D hantro_g1_vp8_dec_run, + .reset =3D hantro_g1_reset, + .init =3D hantro_vp8_dec_init, + .exit =3D hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] =3D { + .run =3D hantro_g1_h264_dec_run, + .reset =3D hantro_g1_reset, + .init =3D hantro_h264_dec_init, + .exit =3D hantro_h264_dec_exit, + }, +}; + +static const struct hantro_irq stm32mp25_irqs[] =3D { + { "vdec", hantro_g1_irq }, +}; + +static const char * const stm32mp25_clk_names[] =3D { "vdec-clk" }; + +const struct hantro_variant stm32mp25_vdec_variant =3D { + .dec_fmts =3D stm32mp25_vdec_fmts, + .num_dec_fmts =3D ARRAY_SIZE(stm32mp25_vdec_fmts), + .codec =3D HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops =3D stm32mp25_vdec_codec_ops, + .irqs =3D stm32mp25_irqs, + .num_irqs =3D ARRAY_SIZE(stm32mp25_irqs), + .clk_names =3D stm32mp25_clk_names, + .num_clocks =3D ARRAY_SIZE(stm32mp25_clk_names), +}; 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Wed, 20 Dec 2023 16:27:36 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v4 3/5] media: hantro: add support for STM32MP25 VENC Date: Wed, 20 Dec 2023 16:27:30 +0100 Message-ID: <20231220152732.2138260-4-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> References: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_09,2023-12-20_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add support for STM32MP25 VENC video hardware encoder. Support of JPEG encoding. VENC has its own reset/clock/irq. Signed-off-by: Hugues Fruchet Reviewed-by: Nicolas Dufresne --- drivers/media/platform/verisilicon/Makefile | 3 +- .../media/platform/verisilicon/hantro_drv.c | 1 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_venc_hw.c | 115 ++++++++++++++++++ 4 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_venc_hw.c diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/pl= atform/verisilicon/Makefile index 5854e0f0dd32..3bf43fdbedc1 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -41,4 +41,5 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) +=3D \ sunxi_vpu_hw.o =20 hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) +=3D \ - stm32mp25_vdec_hw.o + stm32mp25_vdec_hw.o \ + stm32mp25_venc_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/medi= a/platform/verisilicon/hantro_drv.c index 2db27c333924..4d97a8ac03de 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -736,6 +736,7 @@ static const struct of_device_id of_hantro_match[] =3D { #endif #ifdef CONFIG_VIDEO_HANTRO_STM32MP25 { .compatible =3D "st,stm32mp25-vdec", .data =3D &stm32mp25_vdec_variant,= }, + { .compatible =3D "st,stm32mp25-venc", .data =3D &stm32mp25_venc_variant,= }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media= /platform/verisilicon/hantro_hw.h index b7eccc1a96fc..70c72e9d11d5 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -407,6 +407,7 @@ extern const struct hantro_variant rk3588_vpu981_varian= t; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_variant stm32mp25_vdec_variant; +extern const struct hantro_variant stm32mp25_venc_variant; =20 extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c b/drive= rs/media/platform/verisilicon/stm32mp25_venc_hw.c new file mode 100644 index 000000000000..0ff0f073b922 --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 VENC video encoder driver + * + * Copyright (C) STMicroelectronics SA 2022 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include +#include +#include + +#include "hantro.h" +#include "hantro_jpeg.h" +#include "hantro_h1_regs.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_venc_fmts[] =3D { + { + .fourcc =3D V4L2_PIX_FMT_YUV420M, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_YUV420P, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV12M, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_YUV420SP, + }, + { + .fourcc =3D V4L2_PIX_FMT_YUYV, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_YUYV422, + }, + { + .fourcc =3D V4L2_PIX_FMT_UYVY, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_UYVY422, + }, + { + .fourcc =3D V4L2_PIX_FMT_JPEG, + .codec_mode =3D HANTRO_MODE_JPEG_ENC, + .max_depth =3D 2, + .header_size =3D JPEG_HEADER_SIZE, + .frmsize =3D { + .min_width =3D 96, + .max_width =3D FMT_4K_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D 96, + .max_height =3D FMT_4K_HEIGHT, + .step_height =3D MB_DIM, + }, + }, +}; + +static irqreturn_t stm32mp25_venc_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu =3D dev_id; + enum vb2_buffer_state state; + u32 status; + + status =3D vepu_read(vpu, H1_REG_INTERRUPT); + state =3D (status & H1_REG_INTERRUPT_FRAME_RDY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +static void stm32mp25_venc_reset(struct hantro_ctx *ctx) +{ +} + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_venc_codec_ops[] =3D { + [HANTRO_MODE_JPEG_ENC] =3D { + .run =3D hantro_h1_jpeg_enc_run, + .reset =3D stm32mp25_venc_reset, + .done =3D hantro_h1_jpeg_enc_done, + }, +}; + +/* + * Variants. + */ + +static const struct hantro_irq stm32mp25_venc_irqs[] =3D { + { "venc", stm32mp25_venc_irq }, +}; + +static const char * const stm32mp25_venc_clk_names[] =3D { + "venc-clk" +}; + +const struct hantro_variant stm32mp25_venc_variant =3D { + .enc_fmts =3D stm32mp25_venc_fmts, + .num_enc_fmts =3D ARRAY_SIZE(stm32mp25_venc_fmts), + .codec =3D HANTRO_JPEG_ENCODER, + .codec_ops =3D stm32mp25_venc_codec_ops, + .irqs =3D stm32mp25_venc_irqs, + .num_irqs =3D ARRAY_SIZE(stm32mp25_venc_irqs), + .clk_names =3D stm32mp25_venc_clk_names, + .num_clocks =3D ARRAY_SIZE(stm32mp25_venc_clk_names) +}; + --=20 2.25.1 From nobody Fri Dec 19 14:08:10 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7625E40BF6; Wed, 20 Dec 2023 15:27:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="KhtbhWjO" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKA1oHs026362; Wed, 20 Dec 2023 16:27:38 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=iSjyXXBlLU8CmpUXVSZCKnI2Y7L6CFxxoTsOMTlPK98=; b=Kh tbhWjOf5LxMDL1WJLS6C/KBUirveBb7F/SbLsuGQwDzoO4gAcOfUIts4cWjzWjZx u7Dcpk8spLwnZna+8WcwN9ymmCrpYs5a6Pv3KtguYn+JD3yeLGWb66hv9ygTS2zr c15Rc4JkP1RxH6fGu+pOvL7JqsHxP/xffuz9myWpHSf1uo0oGVHeXYXYS8jXDg0o RqGbf1bxJZOcaqpEw6ibUfTVHTgV2PLR/V2w0Hd4jXvx135epz+WlUOPkc0wRlg+ vn+JzPplBC0iprCy6AM+vhCxueqYr6QcCNU7DyGy95+MsUaT/nh7R9iEzxruGfUZ 0DDtGg59vhoHqk5e3BcA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v126m2ppv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:27:38 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DFE65100057; Wed, 20 Dec 2023 16:27:37 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D449921ED29; Wed, 20 Dec 2023 16:27:37 +0100 (CET) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 16:27:37 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v4 4/5] arm64: dts: st: add video decoder support to stm32mp255 Date: Wed, 20 Dec 2023 16:27:31 +0100 Message-ID: <20231220152732.2138260-5-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> References: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_09,2023-12-20_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add VDEC hardware video decoder support to STM32MP255. Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 96859d098ef8..8fc7e9199499 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ ck_icn_ls_mcu: ck-icn-ls-mcu { compatible =3D "fixed-clock"; clock-frequency =3D <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index e6fa596211f5..aea5096dac3c 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,4 +6,14 @@ #include "stm32mp253.dtsi" =20 / { + soc@0 { + rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible =3D "st,stm32mp25-vdec"; + reg =3D <0x480d0000 0x3c8>; + interrupts =3D ; + clocks =3D <&ck_icn_p_vdec>; + }; + }; + }; }; --=20 2.25.1 From nobody Fri Dec 19 14:08:10 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC25C405EF; Wed, 20 Dec 2023 15:28:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="RHjxNMA6" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKAf2YH011895; Wed, 20 Dec 2023 16:28:39 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=gOTJOkgkUXjyDgxkghIjHED6KsoYJ6xYXo9usGGB+Xk=; b=RH jxNMA6pwf3Oh7gds5r32LGVowam+bdSUMq+QvqZ8P4GbpbCVvh0YUvvA6to/oczM 6SkM7c+Zr66tofKFwkc+ZaEDTB/r/q33kgUa4Xs5iciAMoBkFTQHB4/qreu9C1gl hKe+S5mC9bf/5yu5INzFmrs6/LZx2uAyZCX8FijJtTIbcUOkLSophylMsITwUi23 YiI/c9T7Fi3QPRAP4e2d0TTn66IIMFfmnaH+aOqn4s1dJ2+aQftQwn7ECFOkLy2f QlaP/QATCJxal+tLtr1XV8KllRFW8tKKj6WZlHxVUJcUzO5VmWBUAUCXlhsi+Qfq dTUx3ywdPFjhmNjxnYaQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v13nhhvuc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:28:39 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BB3C1100057; Wed, 20 Dec 2023 16:28:38 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AF65121ED2E; Wed, 20 Dec 2023 16:28:38 +0100 (CET) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 16:28:38 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v4 5/5] arm64: dts: st: add video encoder support to stm32mp255 Date: Wed, 20 Dec 2023 16:27:32 +0100 Message-ID: <20231220152732.2138260-6-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> References: <20231220152732.2138260-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_09,2023-12-20_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add VENC hardware video encoder support to STM32MP255. Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8fc7e9199499..5dd4f3580a60 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -58,6 +58,12 @@ ck_icn_p_vdec: ck-icn-p-vdec { compatible =3D "fixed-clock"; clock-frequency =3D <200000000>; }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index aea5096dac3c..17f197c5b22b 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -14,6 +14,13 @@ vdec: vdec@480d0000 { interrupts =3D ; clocks =3D <&ck_icn_p_vdec>; }; + + venc: venc@480e0000 { + compatible =3D "st,stm32mp25-venc"; + reg =3D <0x480e0000 0x800>; + interrupts =3D ; + clocks =3D <&ck_icn_ls_mcu>; + }; }; }; }; --=20 2.25.1