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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343A.mail.protection.outlook.com (10.167.18.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7113.14 via Frontend Transport; Wed, 20 Dec 2023 15:16:21 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 20 Dec 2023 09:16:17 -0600 From: Nikunj A Dadhania To: , , , CC: , , , , , , , , Subject: [PATCH v7 16/16] x86/sev: Enable Secure TSC for SNP guests Date: Wed, 20 Dec 2023 20:43:58 +0530 Message-ID: <20231220151358.2147066-17-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231220151358.2147066-1-nikunj@amd.com> References: <20231220151358.2147066-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|SJ1PR12MB6123:EE_ X-MS-Office365-Filtering-Correlation-Id: e0cb5b82-5134-49b5-b398-08dc016e9fd3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2023 15:16:21.8468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0cb5b82-5134-49b5-b398-08dc016e9fd3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6123 Content-Type: text/plain; charset="utf-8" Now that all the required plumbing is done for enabling SNP Secure TSC feature, add Secure TSC to snp features present list. Set the CPUID feature bit (X86_FEATURE_SNP_SECURE_TSC) when SNP guest is started with Secure TSC. Signed-off-by: Nikunj A Dadhania Tested-by: Peter Gonda --- arch/x86/boot/compressed/sev.c | 3 ++- arch/x86/mm/mem_encrypt.c | 10 ++++++++-- arch/x86/mm/mem_encrypt_amd.c | 4 +++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 454acd7a2daf..2829908602e5 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -375,7 +375,8 @@ static void enforce_vmpl0(void) * by the guest kernel. As and when a new feature is implemented in the * guest kernel, a corresponding bit should be added to the mask. */ -#define SNP_FEATURES_PRESENT MSR_AMD64_SNP_DEBUG_SWAP +#define SNP_FEATURES_PRESENT (MSR_AMD64_SNP_DEBUG_SWAP | \ + MSR_AMD64_SNP_SECURE_TSC) =20 u64 snp_get_unsupported_features(u64 status) { diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index d5bcd63211de..b0db76dc4a9d 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -70,8 +70,14 @@ static void print_mem_encrypt_feature_info(void) pr_cont(" SEV-ES"); =20 /* Secure Nested Paging */ - if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) - pr_cont(" SEV-SNP"); + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) { + pr_cont(" SEV-SNP\n"); + pr_cont("SNP Features active: "); + + /* SNP Secure TSC */ + if (cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) + pr_cont(" SECURE-TSC"); + } =20 pr_cont("\n"); } diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index cc936999efc8..7ee0a537a22e 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -500,8 +500,10 @@ void __init sme_early_init(void) ia32_disable(); =20 /* Mark the TSC as reliable when Secure TSC is enabled */ - if (sev_status & MSR_AMD64_SNP_SECURE_TSC) + if (sev_status & MSR_AMD64_SNP_SECURE_TSC) { + setup_force_cpu_cap(X86_FEATURE_SNP_SECURE_TSC); setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + } } =20 void __init mem_encrypt_free_decrypted_mem(void) --=20 2.34.1