From nobody Fri Sep 20 05:47:45 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE460374D1; Wed, 20 Dec 2023 13:33:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="xtpP4bgf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1703079189; bh=/UPfNwo0qoGJbrXtvl2TR/jus2hvpz31Qe5IC0w5A2c=; h=From:To:Cc:Subject:Date:From; b=xtpP4bgflfX1fY3Td2eH9fzxt0R8XHPB2Ys/fVeu10em5VQI3vV1hsRTjFXSppnkF ceuac2A+CKLBbmwW0Oxegbd+RjBKJJzHJILBfY04dkkFLu99ri8LX+rWfgSLtV31tC 4wR698rKUKmyjvNylnfZj52cooP+7cKSMqSnlrXS8HAW48LVvs31Oz5omyzkeqbkx2 aZlpsEAD3eVAhLQaoH9Jqn7FMoHg5WptJo+VvdACwUCcEkAA2dEdEPdYPdAwynfCCd wryarHvNPy849UyTaU+H1NLHWarHUvpl87I4l3ljo7ebtUHJ9aMVB+HOxZrLvSn1D6 xC+eAn3hrFBMg== Received: from eugen-station.. (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: ehristev) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 2EAD93781F8C; Wed, 20 Dec 2023 13:33:08 +0000 (UTC) From: Eugen Hristev To: angelogioacchino.delregno@collabora.com, linux-mediatek@lists.infradead.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, kernel@collabora.com, eugen.hristev@collabora.com, Yunfei Dong , Allen-KH Cheng , Hsin-Yi Wang Subject: [PATCH] arm64: dts: mediatek: mt8186: Add video decoder device nodes Date: Wed, 20 Dec 2023 15:33:02 +0200 Message-Id: <20231220133302.39411-1-eugen.hristev@collabora.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yunfei Dong Add mt8186 video decoder device nodes. Signed-off-by: Yunfei Dong Signed-off-by: Allen-KH Cheng Reviewed-by: Hsin-Yi Wang [eugen.hristev@collabora.com: minor cleanup] Signed-off-by: Eugen Hristev Reviewed-by: AngeloGioacchino Del Regno --- I based this commit on top of the video encoder patch series. arch/arm64/boot/dts/mediatek/mt8186.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index ebd07bf3d9d2..e451b6c8cd9e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1959,6 +1959,43 @@ larb11: smi@1582e000 { power-domains =3D <&spm MT8186_POWER_DOMAIN_IMG2>; }; =20 + video_decoder: video-decoder@16000000 { + compatible =3D "mediatek,mt8186-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + iommus =3D <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>; + mediatek,scp =3D <&scp>; + + vcodec_core: video-codec@16025000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x16025000 0 0x1000>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&topckgen CLK_TOP_UNIVPLL_D3>; + clock-names =3D "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + }; + larb4: smi@1602e000 { compatible =3D "mediatek,mt8186-smi-larb"; reg =3D <0 0x1602e000 0 0x1000>; --=20 2.34.1