From nobody Fri Sep 20 06:28:55 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8D922099; Wed, 20 Dec 2023 10:39:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="bLiBwrOi" X-UUID: 091615869f2411eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EKSwPiRLuw7KYRnjFJ15A32RS6dXDQz7YbePkJNXv/E=; b=bLiBwrOiMfQJp43NCL98H5txpZOFkOzSnlvD8BEyayXk+NbLAtl5ugNsj2eVGEKBlpPuuILoQKgqYeJd/3PkhNyy43pZlt0YPSHQlkwkiJbeFerEAmPPzRaY1t3WIK8jnHpBESOB3CTVvQ2YjMwB92tsOsgHpwoLAHlRPH5waDA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:0a49ffa1-02e8-415e-9e6a-18e17794a619,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:4097618d-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 091615869f2411eea5db2bebc7c28f94-20231220 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 974429302; Wed, 20 Dec 2023 18:39:21 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:39:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:39:20 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Srinivas Kandagatla CC: , , , , William-tw Lin Subject: [PATCH v3 1/3] arm64: dts: Add node for chip info driver Date: Wed, 20 Dec 2023 18:38:59 +0800 Message-ID: <20231220103901.22180-2-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220103901.22180-1-william-tw.lin@mediatek.com> References: <20231220103901.22180-1-william-tw.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.895700-8.000000 X-TMASE-MatchedRID: jhJi18RLqAJbbwmb1mOeyx+WEMjoO9WWTJDl9FKHbrk3nZaS9VtZrqPF jJEFr+olwXCBO/GKkVr3FLeZXNZS4CiM3WUt6LtFNK4pZj/Hg0kjmtV8Q/0SEs6K5vv4EqP1JoX /CQCmyyMFoF08IxPyBtL3VNJRBhun0YfblHonBjiRVhCh489z1mkW5gEw17GTeZUpm6wun3ba/0 6NhYDa4wyzCDjlUx89djekYOaiKTo= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.895700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 98ED5DAA45140FF0638775DBDE6E76C16BC381C1F39C3431CDEDB8C1ECEBE6992000:8 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dts node for socinfo retrieval for the following projects: MT8173, MT8183, MT8186, MT8192, MT8195 Signed-off-by: William-tw Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 9 +++++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 ++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++ 5 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index c47d7d900f28..06916e60679a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -590,6 +590,15 @@ reg =3D <0 0x10206000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + socinfo_data1: socinfo-data1@40 { + reg =3D <0x040 0x4>; + }; + + socinfo_data2: socinfo-data2@44 { + reg =3D <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg =3D <0x528 0xc>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 976dc968b3ca..d39c25db042e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1585,6 +1585,15 @@ reg =3D <0 0x11f10000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + socinfo_data1: socinfo-data1@4c { + reg =3D <0x04c 0x4>; + }; + + socinfo_data2: socinfo-data2@60 { + reg =3D <0x060 0x4>; + }; + thermal_calibration: calib@180 { reg =3D <0x180 0xc>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index df0c04f2ba1d..0e2f6fe14081 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1672,6 +1672,10 @@ reg =3D <0x59c 0x4>; bits =3D <0 3>; }; + + socinfo_data1: socinfo-data1@7a0 { + reg =3D <0x7a0 0x4>; + }; }; =20 mipi_tx0: dsi-phy@11cc0000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 69f4cded5dbb..a329b430429f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1120,6 +1120,14 @@ #address-cells =3D <1>; #size-cells =3D <1>; =20 + socinfo_data1: socinfo-data1@44 { + reg =3D <0x044 0x4>; + }; + + socinfo_data2: socinfo-data2@50 { + reg =3D <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg =3D <0x1c0 0x58>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index e0ac2e9f5b72..f1926a6afa8f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1686,6 +1686,9 @@ lvts_efuse_data2: lvts2-calib@1d0 { reg =3D <0x1d0 0x38>; }; + socinfo_data1: socinfo-data1@7a0 { + reg =3D <0x7a0 0x4>; + }; }; =20 u3phy2: t-phy@11c40000 { --=20 2.18.0 From nobody Fri Sep 20 06:28:55 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A73722311; Wed, 20 Dec 2023 10:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="F+z4toS6" X-UUID: 0a1fb9469f2411eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rAXaVDDN3GJbjJ+A+RI0E/Hku5aIiiTtLCoa0Akqi/A=; b=F+z4toS69u1Fddes7HlpEnIEVDGb08LrQK6u6t5ESitTxHBQkx0Iq/kNm3HQpp4OLmBGl+INNVWX2gl/vvL6ipW9K1hcTOFYZ4XXaOEyJZDHgmEOkIdBPef1PHvd5km3KitdqarpOXX9V0vJDdjRej2yUTvLeUt+DrZge/QtW1Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:43c0e905-13d1-411e-b960-e978b66ec39e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:cc8d7a7e-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 0a1fb9469f2411eea5db2bebc7c28f94-20231220 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 53193792; Wed, 20 Dec 2023 18:39:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:39:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:39:22 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Srinivas Kandagatla CC: , , , , William-tw Lin Subject: [PATCH v3 2/3] soc: mediatek: mtk-socinfo: Add driver for getting chip information Date: Wed, 20 Dec 2023 18:39:00 +0800 Message-ID: <20231220103901.22180-3-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220103901.22180-1-william-tw.lin@mediatek.com> References: <20231220103901.22180-1-william-tw.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for socinfo retrieval. This patch includes the following: 1. mtk-socinfo driver for chip info retrieval 2. Related changes to Makefile and Kconfig Signed-off-by: William-tw Lin --- drivers/soc/mediatek/Kconfig | 8 ++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-socinfo.c | 186 +++++++++++++++++++++++++++++ 3 files changed, 195 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-socinfo.c diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 0810b5b0c688..f34d93977ba6 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -68,4 +68,12 @@ config MTK_SVS chip process corner, temperatures and other factors. Then DVFS driver could apply SVS bank voltage to PMIC/Buck. =20 +config MTK_SOCINFO + tristate "MediaTek SoC Information" + default y + help + The MediaTek SoC Information (mtk-socinfo) driver provides + information about the SoC to the userspace including the + manufacturer name, marketing name and soc name. + endmenu diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 9d3ce7878c5c..6830512848fd 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_MTK_REGULATOR_COUPLER) +=3D mtk-regulator-coup= ler.o obj-$(CONFIG_MTK_MMSYS) +=3D mtk-mmsys.o obj-$(CONFIG_MTK_MMSYS) +=3D mtk-mutex.o obj-$(CONFIG_MTK_SVS) +=3D mtk-svs.o +obj-$(CONFIG_MTK_SOCINFO) +=3D mtk-socinfo.o diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-= socinfo.c new file mode 100644 index 000000000000..4a257b5c8eda --- /dev/null +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_SOCINFO_ENTRY(_soc_name, _segment_name, _marketing_name, _cell= _data1, _cell_data2) {\ + .soc_name =3D _soc_name, \ + .segment_name =3D _segment_name, \ + .marketing_name =3D _marketing_name, \ + .cell_data =3D {_cell_data1, _cell_data2} \ +} +#define CELL_NOT_USED (0xFFFFFFFF) +#define MAX_CELLS (2) + +struct mtk_socinfo { + struct device *dev; + struct name_data *name_data; + struct socinfo_data *socinfo_data; + struct soc_device *soc_dev; +}; + +struct socinfo_data { + char *soc_name; + char *segment_name; + char *marketing_name; + u32 cell_data[MAX_CELLS]; +}; + +static const char *cell_names[MAX_CELLS] =3D {"socinfo-data1", "socinfo-da= ta2"}; + +static struct socinfo_data socinfo_data_table[] =3D { + MTK_SOCINFO_ENTRY("MT8173", "MT8173V/AC", "MT8173", 0x6CA20004, 0x1000000= 0), + MTK_SOCINFO_ENTRY("MT8183", "MT8183V/AZA", "Kompanio 500", 0x00010043, 0x= 00000840), + MTK_SOCINFO_ENTRY("MT8186", "MT8186GV/AZA", "Kompanio 520", 0x81861001, C= ELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8186T", "MT8186TV/AZA", "Kompanio 528", 0x81862001, = CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/AZA", "Kompanio 830", 0x81880000, 0= x00000010), + MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/HZA", "Kompanio 830", 0x81880000, 0= x00000011), + MTK_SOCINFO_ENTRY("MT8192", "MT8192V/AZA", "Kompanio 820", 0x00001100, 0x= 00040080), + MTK_SOCINFO_ENTRY("MT8192T", "MT8192V/ATZA", "Kompanio 828", 0x00000100, = 0x000400C0), + MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EZA", "Kompanio 1200", 0x81950300, = CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EHZA", "Kompanio 1200", 0x81950304,= CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EZA", "Kompanio 1380", 0x81950400, = CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EHZA", "Kompanio 1380", 0x81950404,= CELL_NOT_USED), +}; + +static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfo= p) +{ + struct soc_device_attribute *attrs; + static char machine[30] =3D {0}; + static const char *soc_manufacturer =3D "MediaTek"; + + attrs =3D devm_kzalloc(mtk_socinfop->dev, sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENOMEM; + + snprintf(machine, sizeof(machine), "%s (%s)", mtk_socinfop->socinfo_data-= >marketing_name, + mtk_socinfop->socinfo_data->soc_name); + attrs->family =3D soc_manufacturer; + attrs->machine =3D machine; + + mtk_socinfop->soc_dev =3D soc_device_register(attrs); + if (IS_ERR(mtk_socinfop->soc_dev)) + return PTR_ERR(mtk_socinfop->soc_dev); + + dev_info(mtk_socinfop->dev, "%s %s SoC detected.\n", soc_manufacturer, at= trs->machine); + return 0; +} + +static u32 mtk_socinfo_read_cell(struct device *dev, const char *name) +{ + struct nvmem_device *nvmemp; + struct device_node *np =3D dev->of_node; + u32 offset; + u32 cell_val =3D CELL_NOT_USED; + + nvmemp =3D devm_nvmem_device_get(dev, "mtk-efuse0"); + if (IS_ERR(nvmemp)) + goto out; + + np =3D of_find_node_by_name(NULL, name); + if (!np) + goto out; + + if (of_property_read_u32_index(np, "reg", 0, &offset)) + goto out; + + nvmem_device_read(nvmemp, offset, sizeof(cell_val), &cell_val); + + nvmem_device_put(nvmemp); + +out: + return cell_val; +} + +static int mtk_socinfo_get_socinfo_data(struct mtk_socinfo *mtk_socinfop) +{ + unsigned int i, j; + unsigned int num_cell_data =3D 0; + u32 cell_data[MAX_CELLS] =3D {0}; + bool match_socinfo; + int match_socinfo_index =3D -1; + + for (i =3D 0; i < MAX_CELLS; i++) { + cell_data[i] =3D mtk_socinfo_read_cell(mtk_socinfop->dev, cell_names[i]); + if (cell_data[i] !=3D CELL_NOT_USED) + num_cell_data++; + else + break; + } + + if (!num_cell_data) + return -ENOENT; + + for (i =3D 0; i < ARRAY_SIZE(socinfo_data_table); i++) { + match_socinfo =3D true; + for (j =3D 0; j < num_cell_data; j++) { + if (cell_data[j] !=3D socinfo_data_table[i].cell_data[j]) { + match_socinfo =3D false; + break; + } + } + if (match_socinfo) { + mtk_socinfop->socinfo_data =3D &(socinfo_data_table[i]); + match_socinfo_index =3D i; + break; + } + } + + return match_socinfo_index >=3D 0 ? match_socinfo_index : -ENOENT; +} + +static int mtk_socinfo_probe(struct platform_device *pdev) +{ + struct mtk_socinfo *mtk_socinfop; + int ret; + + mtk_socinfop =3D devm_kzalloc(&pdev->dev, sizeof(*mtk_socinfop), GFP_KERN= EL); + if (!mtk_socinfop) + return -ENOMEM; + + mtk_socinfop->dev =3D &pdev->dev; + + ret =3D mtk_socinfo_get_socinfo_data(mtk_socinfop); + if (ret < 0) + return dev_err_probe(mtk_socinfop->dev, ret, "Failed to get socinfo data= \n"); + + ret =3D mtk_socinfo_create_socinfo_node(mtk_socinfop); + if (ret) + return dev_err_probe(mtk_socinfop->dev, ret, "Cannot create node\n"); + + platform_set_drvdata(pdev, mtk_socinfop); + return 0; +} + +static void mtk_socinfo_remove(struct platform_device *pdev) +{ + struct mtk_socinfo *mtk_socinfop =3D platform_get_drvdata(pdev); + + soc_device_unregister(mtk_socinfop->soc_dev); +} + +static struct platform_driver mtk_socinfo =3D { + .probe =3D mtk_socinfo_probe, + .remove_new =3D mtk_socinfo_remove, + .driver =3D { + .name =3D "mtk-socinfo", + }, +}; +builtin_platform_driver(mtk_socinfo); + +MODULE_AUTHOR("William-TW LIN "); +MODULE_DESCRIPTION("MediaTek socinfo driver"); +MODULE_LICENSE("GPL"); --=20 2.18.0 From nobody Fri Sep 20 06:28:55 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 564E42231D; Wed, 20 Dec 2023 10:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tHif4mT0" X-UUID: 0b9357069f2411eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6nc2v4XK4GgMWiKrx1TmkatyK/XnMtUXXUmJveqsh50=; b=tHif4mT0gJNrd9ufcrKnjj6SMik67nKPPEDRg1HHAuz7lY9ZorFaUNKP5L4ftznugP/LGZ9DipNlyOv8bQ0kuhH1xB9Wgvdl9oPmqwy7xPpsx6nFUMiqpMN6Jf2CGVy4OgXOe5eNaLAdZVCENoQCyigrxryNSfYoVnszGCziGLQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:961659b4-ae08-4cbd-b76d-95f1f3e37dbf,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:d5ff4b2e-1ab8-4133-9780-81938111c800,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 0b9357069f2411eeba30773df0976c77-20231220 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 680687742; Wed, 20 Dec 2023 18:39:25 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:39:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:39:24 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Srinivas Kandagatla CC: , , , , William-tw Lin Subject: [PATCH v3 3/3] nvmem: mtk-efuse: Modify driver for getting chip information Date: Wed, 20 Dec 2023 18:39:01 +0800 Message-ID: <20231220103901.22180-4-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220103901.22180-1-william-tw.lin@mediatek.com> References: <20231220103901.22180-1-william-tw.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.994400-8.000000 X-TMASE-MatchedRID: 4UDH+/Xdc14QoD+Lr/yRKcnUT+eskUQPCt59Uh3p/NVcU0dNErOD+vlY oV6p/cSxYZon4ysgRFrD3fsd5FfxU5zDsl2JUMqfjFUG+PWNtyOWHGENdT+VP5soi2XrUn/Jn6K dMrRsL14qtq5d3cxkNRqXnrxrKCOXjBIzy2yVj36aFhDRX/XeG+7AwkxltPESpGOM5kASXvdoTE NRNo092nMWWXdH8XCFPKAPShj3y9+iL7s3pM/O5VsfT8+GQE6MF0aD5ljt43pMcHZD6gqu7wxMj fifIXfowkvVoA11Twp+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.994400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: DF501D5E8CD1E5A7AAF290735A49D2F4108BF1F346C084B579BE8F49EED3493E2000:8 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Retrieval of soc info is needed. This patch includes the following: 1. Register socinfo device in mtk-efuse.c Signed-off-by: William-tw Lin --- drivers/nvmem/mtk-efuse.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index 84f05b40a411..3914e039e288 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -68,6 +68,7 @@ static int mtk_efuse_probe(struct platform_device *pdev) struct nvmem_config econfig =3D {}; struct mtk_efuse_priv *priv; const struct mtk_efuse_pdata *pdata; + struct platform_device *socinfo; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -85,11 +86,19 @@ static int mtk_efuse_probe(struct platform_device *pdev) econfig.size =3D resource_size(res); econfig.priv =3D priv; econfig.dev =3D dev; + econfig.name =3D "mtk-efuse"; if (pdata->uses_post_processing) econfig.fixup_dt_cell_info =3D &mtk_efuse_fixup_dt_cell_info; nvmem =3D devm_nvmem_register(dev, &econfig); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); =20 - return PTR_ERR_OR_ZERO(nvmem); + socinfo =3D platform_device_register_data(&pdev->dev, "mtk-socinfo", + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(socinfo)) + dev_info(dev, "MediaTek SoC Information will be unavailable\n"); + + return 0; } =20 static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata =3D { --=20 2.18.0