From nobody Wed Nov 13 02:17:16 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 439BF2031D; Wed, 20 Dec 2023 10:18:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qHDUzL5/" X-UUID: 259193f09f2111eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hyYnoqNGoSTTbIxf1opsH0bdkk2hskuSdMmZlWWvdeE=; b=qHDUzL5/JfKYFu3YH6r+JhuHgY/dJcAr/Q4UTEIunt9WpjJAVoBQYw/jDBFHfuJ8fxQnGdqYEPLRdX4gnu22ZGJq3s2QTpekTEkCczlcT7H5wr9TEoMzJ/GWR2l8XuYzWt/Le6VEhl4MGIARi9rcfBwF3wgvf4JJB7oC8SjRD4Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:aae6af37-1da0-4fb6-b405-729e74cd3795,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:30da4b2e-1ab8-4133-9780-81938111c800,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 259193f09f2111eea5db2bebc7c28f94-20231220 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 235987117; Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:40 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 08/12] media: platform: mtk-mdp3: add support for blending multiple components Date: Wed, 20 Dec 2023 18:18:34 +0800 Message-ID: <20231220101838.21510-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.879000-8.000000 X-TMASE-MatchedRID: KlFhDc9v5J5ILSVPxvZJcHV895e/Bd2J1KoSW5Ji1Xv/evmlVf9xZpeS PuHyHNrhlTJXKqh1ne29cOdjc/43len2wHlv5vGudXu122+iJtoEa8g1x8eqF08vg1FXaj1omPw bEvJgAefCFUdoPtcptMfW2dzExL8C/16F1o/rJO7hG1IOMb7PsH0tCKdnhB58I/9UW5M5dRN3A3 6JhZ4tNfcUt5lc1lLgjMejjvPkBr7EKputfZBfQMUedzTwMFPo5ATKJjWFuPBd9A+8AE1s3zMr+ lwPT/UeRAKRId7FA5h8TTcKUOgXlBcaD2m2fFe6RBRiZYZplB95lSmbrC6fdtr/To2FgNrjDLMI OOVTHz2nbLeYgH6K31Zca9RSYo/b X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.879000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 09D00D7E8EFE7674FAFAE6BB8D6E4A00D9443F2C780E5841E18C2F853C72CA532000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Certain chips can combine several components to form complex virtual units with advanced functions. These components require simultaneous configuration of their MODs and clocks. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 10 ++++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 29 +++++++++++++++++-- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 7 +++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index a81caf5f472c..f0c5f5abeb23 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -110,17 +110,25 @@ static int mdp_path_subfrm_require(const struct mdp_p= ath *path, /* Set mutex mod */ for (index =3D 0; index < num_comp; index++) { s32 inner_id =3D MDP_COMP_NONE; + const u32 *mutex_idx; + const struct mdp_comp_blend *b; =20 if (CFG_CHECK(MT8183, p_id)) inner_id =3D CFG_GET(MT8183, path->config, components[index].type); if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; + ctx =3D &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; + + mutex_idx =3D data->mdp_mutex_table_idx; id =3D ctx->comp->public_id; - mtk_mutex_write_mod(mutex, data->mdp_mutex_table_idx[id], false); + mtk_mutex_write_mod(mutex, mutex_idx[id], false); =20 + b =3D &data->comp_data[id].blend; + if (b && b->aid_mod) + mtk_mutex_write_mod(mutex, mutex_idx[b->b_id], false); } =20 mtk_mutex_write_sof(mutex, MUTEX_SOF_IDX_SINGLE_MODE); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-comp.c index ed6092e1666f..e97630b7867c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -864,12 +864,26 @@ int mdp_comp_clocks_on(struct device *dev, struct mdp= _comp *comps, int num) int i, ret; =20 for (i =3D 0; i < num; i++) { + struct mdp_dev *m =3D comps[i].mdp_dev; + enum mtk_mdp_comp_id id; + const struct mdp_comp_blend *b; + /* Bypass the dummy component*/ - if (!comps[i].mdp_dev) + if (!m) continue; + ret =3D mdp_comp_clock_on(dev, &comps[i]); if (ret) return ret; + + id =3D comps[i].public_id; + b =3D &m->mdp_data->comp_data[id].blend; + + if (b && b->aid_clk) { + ret =3D mdp_comp_clock_on(dev, m->comp[b->b_id]); + if (ret) + return ret; + } } =20 return 0; @@ -880,10 +894,21 @@ void mdp_comp_clocks_off(struct device *dev, struct m= dp_comp *comps, int num) int i; =20 for (i =3D 0; i < num; i++) { + struct mdp_dev *m =3D comps[i].mdp_dev; + enum mtk_mdp_comp_id id; + const struct mdp_comp_blend *b; + /* Bypass the dummy component*/ - if (!comps[i].mdp_dev) + if (!m) continue; + mdp_comp_clock_off(dev, &comps[i]); + + id =3D comps[i].public_id; + b =3D &m->mdp_data->comp_data[id].blend; + + if (b && b->aid_clk) + mdp_comp_clock_off(dev, m->comp[b->b_id]); } } =20 diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-comp.h index e6cbc6ab6bae..3e5d2da1c807 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -201,9 +201,16 @@ struct mdp_comp_info { u32 dts_reg_ofst; }; =20 +struct mdp_comp_blend { + enum mtk_mdp_comp_id b_id; + bool aid_mod; + bool aid_clk; +}; + struct mdp_comp_data { struct mdp_comp_match match; struct mdp_comp_info info; + struct mdp_comp_blend blend; }; =20 struct mdp_comp_ops; --=20 2.18.0