From nobody Thu Nov 14 05:14:55 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F6E420DCB; Wed, 20 Dec 2023 10:18:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="NlJl7D44" X-UUID: 25c3db589f2111eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6Xw93SJZqwpcvsEq+crui13qYLI2pKWup24/U893Prc=; b=NlJl7D44HmYL7ozOoNRCgq/TjbmQcbtB2lNkC1nAJDOOaLEpSAyT830BcacuG7QtbEhSCsPr8Is8L/64h/BorpTCCh0Tt0TAuenn72rubSohK1U9VCNiVgx1ShCJ0z4gPxFQTw//VZ+zR0b3lWjYz9vi4Hnm8LhHgLUZrffXTgU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:9edd9ef1-0951-4b49-a492-6d1848e00fb5,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:5c71618d-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 25c3db589f2111eeba30773df0976c77-20231220 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1183766274; Wed, 20 Dec 2023 18:18:41 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:40 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 09/12] media: platform: mtk-mdp3: add mt8195 platform configuration Date: Wed, 20 Dec 2023 18:18:35 +0800 Message-ID: <20231220101838.21510-10-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--9.478000-8.000000 X-TMASE-MatchedRID: DsFl2sNdNIss6cxI7W6yCG3NvezwBrVm6SXuwUgGH0j3dSKTMI31W2b6 PphVtfZg6pizmvbqzYgSnnEBkyExwynPugGsN3p5rDFtme53KvuuiRuR9mCaur/A+0D1to6PMfG c6CCGjvfWyrFkZMcWP1IlPImyJmzuEEBjOlnEA/xtqNUBzYMqpuYQsENyzR2d63RWgrXHe9eU62 zvc1Dlo978LCf5PSaOFfnemUOegIu4c6uEFrThdqIBnfMCFBiCi/ymJ2FVg5Tfc2Xd6VJ+yhFxR 5JQAS6OdfwrmnTJ55PjZYLx9+Z7tR8TzIzimOwPC24oEZ6SpSk6XEE7Yhw4Frp3G3FiGcc6Pbcp nCezGJrWc5pmhLiiJ4NX05/nU791P83vAjhIceg= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--9.478000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: DAF228793A232D2BC6B11F6EAC0933EB7A5F84436809FCE6A2325F038BB36C802000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8195 MDP3 basic configuration in file "mdp_cfg_data.c" and corresponding driver data. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 666 ++++++++++++++++++ .../platform/mediatek/mdp3/mtk-img-ipi.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 36 + .../platform/mediatek/mdp3/mtk-mdp3-core.c | 6 + .../platform/mediatek/mdp3/mtk-mdp3-core.h | 6 + 6 files changed, 716 insertions(+) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/= media/platform/mediatek/mdp3/mdp_cfg_data.c index 3834efe54e17..9ee3931d31e3 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -46,12 +46,91 @@ enum mt8183_mdp_comp_id { MT8183_MDP_COMP_WROT1, /* 25 */ }; =20 +enum mt8195_mdp_comp_id { + /* MT8195 Comp id */ + /* ISP */ + MT8195_MDP_COMP_WPEI =3D 0, + MT8195_MDP_COMP_WPEO, /* 1 */ + MT8195_MDP_COMP_WPEI2, /* 2 */ + MT8195_MDP_COMP_WPEO2, /* 3 */ + + /* MDP */ + MT8195_MDP_COMP_CAMIN, /* 4 */ + MT8195_MDP_COMP_CAMIN2, /* 5 */ + MT8195_MDP_COMP_SPLIT, /* 6 */ + MT8195_MDP_COMP_SPLIT2, /* 7 */ + MT8195_MDP_COMP_RDMA0, /* 8 */ + MT8195_MDP_COMP_RDMA1, /* 9 */ + MT8195_MDP_COMP_RDMA2, /* 10 */ + MT8195_MDP_COMP_RDMA3, /* 11 */ + MT8195_MDP_COMP_STITCH, /* 12 */ + MT8195_MDP_COMP_FG0, /* 13 */ + MT8195_MDP_COMP_FG1, /* 14 */ + MT8195_MDP_COMP_FG2, /* 15 */ + MT8195_MDP_COMP_FG3, /* 16 */ + MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */ + MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */ + MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */ + MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */ + MT8195_MDP_COMP_VPP0_SOUT, /* 21 */ + MT8195_MDP_COMP_VPP1_SOUT, /* 22 */ + MT8195_MDP_COMP_PQ0_SOUT, /* 23 */ + MT8195_MDP_COMP_PQ1_SOUT, /* 24 */ + MT8195_MDP_COMP_HDR0, /* 25 */ + MT8195_MDP_COMP_HDR1, /* 26 */ + MT8195_MDP_COMP_HDR2, /* 27 */ + MT8195_MDP_COMP_HDR3, /* 28 */ + MT8195_MDP_COMP_AAL0, /* 29 */ + MT8195_MDP_COMP_AAL1, /* 30 */ + MT8195_MDP_COMP_AAL2, /* 31 */ + MT8195_MDP_COMP_AAL3, /* 32 */ + MT8195_MDP_COMP_RSZ0, /* 33 */ + MT8195_MDP_COMP_RSZ1, /* 34 */ + MT8195_MDP_COMP_RSZ2, /* 35 */ + MT8195_MDP_COMP_RSZ3, /* 36 */ + MT8195_MDP_COMP_TDSHP0, /* 37 */ + MT8195_MDP_COMP_TDSHP1, /* 38 */ + MT8195_MDP_COMP_TDSHP2, /* 39 */ + MT8195_MDP_COMP_TDSHP3, /* 40 */ + MT8195_MDP_COMP_COLOR0, /* 41 */ + MT8195_MDP_COMP_COLOR1, /* 42 */ + MT8195_MDP_COMP_COLOR2, /* 43 */ + MT8195_MDP_COMP_COLOR3, /* 44 */ + MT8195_MDP_COMP_OVL0, /* 45 */ + MT8195_MDP_COMP_OVL1, /* 46 */ + MT8195_MDP_COMP_PAD0, /* 47 */ + MT8195_MDP_COMP_PAD1, /* 48 */ + MT8195_MDP_COMP_PAD2, /* 49 */ + MT8195_MDP_COMP_PAD3, /* 50 */ + MT8195_MDP_COMP_TCC0, /* 51 */ + MT8195_MDP_COMP_TCC1, /* 52 */ + MT8195_MDP_COMP_WROT0, /* 53 */ + MT8195_MDP_COMP_WROT1, /* 54 */ + MT8195_MDP_COMP_WROT2, /* 55 */ + MT8195_MDP_COMP_WROT3, /* 56 */ + MT8195_MDP_COMP_MERGE2, /* 57 */ + MT8195_MDP_COMP_MERGE3, /* 58 */ + + MT8195_MDP_COMP_VDO0DL0, /* 59 */ + MT8195_MDP_COMP_VDO1DL0, /* 60 */ + MT8195_MDP_COMP_VDO0DL1, /* 61 */ + MT8195_MDP_COMP_VDO1DL1, /* 62 */ +}; + static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] =3D= { [MDP_INFRA_MMSYS] =3D { .compatible =3D "mediatek,mt8183-mmsys" }, [MDP_INFRA_MUTEX] =3D { .compatible =3D "mediatek,mt8183-disp-mutex" }, [MDP_INFRA_SCP] =3D { .compatible =3D "mediatek,mt8183-scp" } }; =20 +static const struct of_device_id mt8195_mdp_probe_infra[MDP_INFRA_MAX] =3D= { + [MDP_INFRA_MMSYS] =3D { .compatible =3D "mediatek,mt8195-vppsys0" }, + [MDP_INFRA_MMSYS2] =3D { .compatible =3D "mediatek,mt8195-vppsys1" }, + [MDP_INFRA_MUTEX] =3D { .compatible =3D "mediatek,mt8195-vpp-mutex" }, + [MDP_INFRA_MUTEX2] =3D { .compatible =3D "mediatek,mt8195-vpp-mutex" }, + [MDP_INFRA_SCP] =3D { .compatible =3D "mediatek,mt8195-scp" } +}; + static const struct mdp_platform_config mt8183_plat_cfg =3D { .rdma_support_10bit =3D true, .rdma_rsz1_sram_sharing =3D true, @@ -62,6 +141,21 @@ static const struct mdp_platform_config mt8183_plat_cfg= =3D { .wrot_event_num =3D 1, }; =20 +static const struct mdp_platform_config mt8195_plat_cfg =3D { + .rdma_support_10bit =3D true, + .rdma_rsz1_sram_sharing =3D false, + .rdma_upsample_repeat_only =3D false, + .rdma_esl_setting =3D true, + .rdma_event_num =3D 4, + .rsz_disable_dcm_small_sample =3D false, + .rsz_etc_control =3D true, + .wrot_filter_constraint =3D false, + .wrot_event_num =3D 4, + .tdshp_hist_num =3D 17, + .tdshp_constrain =3D true, + .tdshp_contour =3D true, +}; + static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] =3D { [MDP_COMP_RDMA0] =3D MUTEX_MOD_IDX_MDP_RDMA0, [MDP_COMP_RSZ0] =3D MUTEX_MOD_IDX_MDP_RSZ0, @@ -73,6 +167,52 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = =3D { [MDP_COMP_CCORR0] =3D MUTEX_MOD_IDX_MDP_CCORR0, }; =20 +static const u32 mt8195_mutex_idx[MDP_MAX_COMP_COUNT] =3D { + [MDP_COMP_RDMA0] =3D MUTEX_MOD_IDX_MDP_RDMA0, + [MDP_COMP_RDMA1] =3D MUTEX_MOD_IDX_MDP_RDMA1, + [MDP_COMP_RDMA2] =3D MUTEX_MOD_IDX_MDP_RDMA2, + [MDP_COMP_RDMA3] =3D MUTEX_MOD_IDX_MDP_RDMA3, + [MDP_COMP_STITCH] =3D MUTEX_MOD_IDX_MDP_STITCH0, + [MDP_COMP_FG0] =3D MUTEX_MOD_IDX_MDP_FG0, + [MDP_COMP_FG1] =3D MUTEX_MOD_IDX_MDP_FG1, + [MDP_COMP_FG2] =3D MUTEX_MOD_IDX_MDP_FG2, + [MDP_COMP_FG3] =3D MUTEX_MOD_IDX_MDP_FG3, + [MDP_COMP_HDR0] =3D MUTEX_MOD_IDX_MDP_HDR0, + [MDP_COMP_HDR1] =3D MUTEX_MOD_IDX_MDP_HDR1, + [MDP_COMP_HDR2] =3D MUTEX_MOD_IDX_MDP_HDR2, + [MDP_COMP_HDR3] =3D MUTEX_MOD_IDX_MDP_HDR3, + [MDP_COMP_AAL0] =3D MUTEX_MOD_IDX_MDP_AAL0, + [MDP_COMP_AAL1] =3D MUTEX_MOD_IDX_MDP_AAL1, + [MDP_COMP_AAL2] =3D MUTEX_MOD_IDX_MDP_AAL2, + [MDP_COMP_AAL3] =3D MUTEX_MOD_IDX_MDP_AAL3, + [MDP_COMP_RSZ0] =3D MUTEX_MOD_IDX_MDP_RSZ0, + [MDP_COMP_RSZ1] =3D MUTEX_MOD_IDX_MDP_RSZ1, + [MDP_COMP_RSZ2] =3D MUTEX_MOD_IDX_MDP_RSZ2, + [MDP_COMP_RSZ3] =3D MUTEX_MOD_IDX_MDP_RSZ3, + [MDP_COMP_MERGE2] =3D MUTEX_MOD_IDX_MDP_MERGE2, + [MDP_COMP_MERGE3] =3D MUTEX_MOD_IDX_MDP_MERGE3, + [MDP_COMP_TDSHP0] =3D MUTEX_MOD_IDX_MDP_TDSHP0, + [MDP_COMP_TDSHP1] =3D MUTEX_MOD_IDX_MDP_TDSHP1, + [MDP_COMP_TDSHP2] =3D MUTEX_MOD_IDX_MDP_TDSHP2, + [MDP_COMP_TDSHP3] =3D MUTEX_MOD_IDX_MDP_TDSHP3, + [MDP_COMP_COLOR0] =3D MUTEX_MOD_IDX_MDP_COLOR0, + [MDP_COMP_COLOR1] =3D MUTEX_MOD_IDX_MDP_COLOR1, + [MDP_COMP_COLOR2] =3D MUTEX_MOD_IDX_MDP_COLOR2, + [MDP_COMP_COLOR3] =3D MUTEX_MOD_IDX_MDP_COLOR3, + [MDP_COMP_OVL0] =3D MUTEX_MOD_IDX_MDP_OVL0, + [MDP_COMP_OVL1] =3D MUTEX_MOD_IDX_MDP_OVL1, + [MDP_COMP_PAD0] =3D MUTEX_MOD_IDX_MDP_PAD0, + [MDP_COMP_PAD1] =3D MUTEX_MOD_IDX_MDP_PAD1, + [MDP_COMP_PAD2] =3D MUTEX_MOD_IDX_MDP_PAD2, + [MDP_COMP_PAD3] =3D MUTEX_MOD_IDX_MDP_PAD3, + [MDP_COMP_TCC0] =3D MUTEX_MOD_IDX_MDP_TCC0, + [MDP_COMP_TCC1] =3D MUTEX_MOD_IDX_MDP_TCC1, + [MDP_COMP_WROT0] =3D MUTEX_MOD_IDX_MDP_WROT0, + [MDP_COMP_WROT1] =3D MUTEX_MOD_IDX_MDP_WROT1, + [MDP_COMP_WROT2] =3D MUTEX_MOD_IDX_MDP_WROT2, + [MDP_COMP_WROT3] =3D MUTEX_MOD_IDX_MDP_WROT3, +}; + static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT]= =3D { [MDP_COMP_WPEI] =3D { {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, MDP_MM_SUBSYS_0}, @@ -148,6 +288,263 @@ static const struct mdp_comp_data mt8183_mdp_comp_dat= a[MDP_MAX_COMP_COUNT] =3D { }, }; =20 +static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT]= =3D { + [MDP_COMP_WPEI] =3D { + {MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_WPEO] =3D { + {MDP_COMP_TYPE_EXTO, 2, MT8195_MDP_COMP_WPEO, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_WPEI2] =3D { + {MDP_COMP_TYPE_WPEI, 1, MT8195_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_WPEO2] =3D { + {MDP_COMP_TYPE_EXTO, 3, MT8195_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_CAMIN] =3D { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0}, + {3, 3, 0} + }, + [MDP_COMP_CAMIN2] =3D { + {MDP_COMP_TYPE_DL_PATH, 1, MT8195_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0}, + {3, 6, 0} + }, + [MDP_COMP_SPLIT] =3D { + {MDP_COMP_TYPE_SPLIT, 0, MT8195_MDP_COMP_SPLIT, MDP_MM_SUBSYS_1}, + {7, 0, 0} + }, + [MDP_COMP_SPLIT2] =3D { + {MDP_COMP_TYPE_SPLIT, 1, MT8195_MDP_COMP_SPLIT2, MDP_MM_SUBSYS_1}, + {7, 0, 0} + }, + [MDP_COMP_RDMA0] =3D { + {MDP_COMP_TYPE_RDMA, 0, MT8195_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0}, + {3, 0, 0} + }, + [MDP_COMP_RDMA1] =3D { + {MDP_COMP_TYPE_RDMA, 1, MT8195_MDP_COMP_RDMA1, MDP_MM_SUBSYS_1}, + {3, 0, 0} + }, + [MDP_COMP_RDMA2] =3D { + {MDP_COMP_TYPE_RDMA, 2, MT8195_MDP_COMP_RDMA2, MDP_MM_SUBSYS_1}, + {3, 0, 0} + }, + [MDP_COMP_RDMA3] =3D { + {MDP_COMP_TYPE_RDMA, 3, MT8195_MDP_COMP_RDMA3, MDP_MM_SUBSYS_1}, + {3, 0, 0} + }, + [MDP_COMP_STITCH] =3D { + {MDP_COMP_TYPE_STITCH, 0, MT8195_MDP_COMP_STITCH, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_FG0] =3D { + {MDP_COMP_TYPE_FG, 0, MT8195_MDP_COMP_FG0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_FG1] =3D { + {MDP_COMP_TYPE_FG, 1, MT8195_MDP_COMP_FG1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_FG2] =3D { + {MDP_COMP_TYPE_FG, 2, MT8195_MDP_COMP_FG2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_FG3] =3D { + {MDP_COMP_TYPE_FG, 3, MT8195_MDP_COMP_FG3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_HDR0] =3D { + {MDP_COMP_TYPE_HDR, 0, MT8195_MDP_COMP_HDR0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_HDR1] =3D { + {MDP_COMP_TYPE_HDR, 1, MT8195_MDP_COMP_HDR1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_HDR2] =3D { + {MDP_COMP_TYPE_HDR, 2, MT8195_MDP_COMP_HDR2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_HDR3] =3D { + {MDP_COMP_TYPE_HDR, 3, MT8195_MDP_COMP_HDR3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_AAL0] =3D { + {MDP_COMP_TYPE_AAL, 0, MT8195_MDP_COMP_AAL0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_AAL1] =3D { + {MDP_COMP_TYPE_AAL, 1, MT8195_MDP_COMP_AAL1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_AAL2] =3D { + {MDP_COMP_TYPE_AAL, 2, MT8195_MDP_COMP_AAL2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_AAL3] =3D { + {MDP_COMP_TYPE_AAL, 3, MT8195_MDP_COMP_AAL3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_RSZ0] =3D { + {MDP_COMP_TYPE_RSZ, 0, MT8195_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_RSZ1] =3D { + {MDP_COMP_TYPE_RSZ, 1, MT8195_MDP_COMP_RSZ1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_RSZ2] =3D { + {MDP_COMP_TYPE_RSZ, 2, MT8195_MDP_COMP_RSZ2, MDP_MM_SUBSYS_1}, + {2, 0, 0}, + {MDP_COMP_MERGE2, true, true} + }, + [MDP_COMP_RSZ3] =3D { + {MDP_COMP_TYPE_RSZ, 3, MT8195_MDP_COMP_RSZ3, MDP_MM_SUBSYS_1}, + {2, 0, 0}, + {MDP_COMP_MERGE3, true, true} + }, + [MDP_COMP_TDSHP0] =3D { + {MDP_COMP_TYPE_TDSHP, 0, MT8195_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP1] =3D { + {MDP_COMP_TYPE_TDSHP, 1, MT8195_MDP_COMP_TDSHP1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP2] =3D { + {MDP_COMP_TYPE_TDSHP, 2, MT8195_MDP_COMP_TDSHP2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP3] =3D { + {MDP_COMP_TYPE_TDSHP, 3, MT8195_MDP_COMP_TDSHP3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_COLOR0] =3D { + {MDP_COMP_TYPE_COLOR, 0, MT8195_MDP_COMP_COLOR0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_COLOR1] =3D { + {MDP_COMP_TYPE_COLOR, 1, MT8195_MDP_COMP_COLOR1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_COLOR2] =3D { + {MDP_COMP_TYPE_COLOR, 2, MT8195_MDP_COMP_COLOR2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_COLOR3] =3D { + {MDP_COMP_TYPE_COLOR, 3, MT8195_MDP_COMP_COLOR3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_OVL0] =3D { + {MDP_COMP_TYPE_OVL, 0, MT8195_MDP_COMP_OVL0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_OVL1] =3D { + {MDP_COMP_TYPE_OVL, 1, MT8195_MDP_COMP_OVL1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_PAD0] =3D { + {MDP_COMP_TYPE_PAD, 0, MT8195_MDP_COMP_PAD0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_PAD1] =3D { + {MDP_COMP_TYPE_PAD, 1, MT8195_MDP_COMP_PAD1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_PAD2] =3D { + {MDP_COMP_TYPE_PAD, 2, MT8195_MDP_COMP_PAD2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_PAD3] =3D { + {MDP_COMP_TYPE_PAD, 3, MT8195_MDP_COMP_PAD3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_TCC0] =3D { + {MDP_COMP_TYPE_TCC, 0, MT8195_MDP_COMP_TCC0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_TCC1] =3D { + {MDP_COMP_TYPE_TCC, 1, MT8195_MDP_COMP_TCC1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_WROT0] =3D { + {MDP_COMP_TYPE_WROT, 0, MT8195_MDP_COMP_WROT0, MDP_MM_SUBSYS_0}, + {1, 0, 0} + }, + [MDP_COMP_WROT1] =3D { + {MDP_COMP_TYPE_WROT, 1, MT8195_MDP_COMP_WROT1, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_WROT2] =3D { + {MDP_COMP_TYPE_WROT, 2, MT8195_MDP_COMP_WROT2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_WROT3] =3D { + {MDP_COMP_TYPE_WROT, 3, MT8195_MDP_COMP_WROT3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_MERGE2] =3D { + {MDP_COMP_TYPE_MERGE, 0, MT8195_MDP_COMP_MERGE2, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_MERGE3] =3D { + {MDP_COMP_TYPE_MERGE, 1, MT8195_MDP_COMP_MERGE3, MDP_MM_SUBSYS_1}, + {1, 0, 0} + }, + [MDP_COMP_PQ0_SOUT] =3D { + {MDP_COMP_TYPE_DUMMY, 0, MT8195_MDP_COMP_PQ0_SOUT, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_PQ1_SOUT] =3D { + {MDP_COMP_TYPE_DUMMY, 1, MT8195_MDP_COMP_PQ1_SOUT, MDP_MM_SUBSYS_1}, + {0, 0, 0} + }, + [MDP_COMP_TO_WARP0MOUT] =3D { + {MDP_COMP_TYPE_DUMMY, 2, MT8195_MDP_COMP_TO_WARP0MOUT, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_TO_WARP1MOUT] =3D { + {MDP_COMP_TYPE_DUMMY, 3, MT8195_MDP_COMP_TO_WARP1MOUT, MDP_MM_SUBSYS_0}, + {0, 0, 0} + }, + [MDP_COMP_TO_SVPP2MOUT] =3D { + {MDP_COMP_TYPE_DUMMY, 4, MT8195_MDP_COMP_TO_SVPP2MOUT, MDP_MM_SUBSYS_1}, + {0, 0, 0} + }, + [MDP_COMP_TO_SVPP3MOUT] =3D { + {MDP_COMP_TYPE_DUMMY, 5, MT8195_MDP_COMP_TO_SVPP3MOUT, MDP_MM_SUBSYS_1}, + {0, 0, 0} + }, + [MDP_COMP_VPP0_SOUT] =3D { + {MDP_COMP_TYPE_PATH, 0, MT8195_MDP_COMP_VPP0_SOUT, MDP_MM_SUBSYS_1}, + {4, 9, 0} + }, + [MDP_COMP_VPP1_SOUT] =3D { + {MDP_COMP_TYPE_PATH, 1, MT8195_MDP_COMP_VPP1_SOUT, MDP_MM_SUBSYS_0}, + {2, 13, 0} + }, + [MDP_COMP_VDO0DL0] =3D { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL0, MDP_MM_SUBSYS_1}, + {1, 15, 0} + }, + [MDP_COMP_VDO1DL0] =3D { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL0, MDP_MM_SUBSYS_1}, + {1, 17, 0} + }, + [MDP_COMP_VDO0DL1] =3D { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL1, MDP_MM_SUBSYS_1}, + {1, 18, 0} + }, + [MDP_COMP_VDO1DL1] =3D { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL1, MDP_MM_SUBSYS_1}, + {1, 16, 0} + }, +}; + static const struct of_device_id mt8183_sub_comp_dt_ids[] =3D { { .compatible =3D "mediatek,mt8183-mdp3-wdma", @@ -159,6 +556,10 @@ static const struct of_device_id mt8183_sub_comp_dt_id= s[] =3D { {} }; =20 +static const struct of_device_id mt8195_sub_comp_dt_ids[] =3D { + {} +}; + /* * All 10-bit related formats are not added in the basic format list, * please add the corresponding format settings before use. @@ -384,6 +785,222 @@ static const struct mdp_format mt8183_formats[] =3D { } }; =20 +static const struct mdp_format mt8195_formats[] =3D { + { + .pixelformat =3D V4L2_PIX_FMT_GREY, + .mdp_color =3D MDP_COLOR_GREY, + .depth =3D { 8 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_RGB565X, + .mdp_color =3D MDP_COLOR_BGR565, + .depth =3D { 16 }, + .row_depth =3D { 16 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_RGB565, + .mdp_color =3D MDP_COLOR_RGB565, + .depth =3D { 16 }, + .row_depth =3D { 16 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_RGB24, + .mdp_color =3D MDP_COLOR_RGB888, + .depth =3D { 24 }, + .row_depth =3D { 24 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_BGR24, + .mdp_color =3D MDP_COLOR_BGR888, + .depth =3D { 24 }, + .row_depth =3D { 24 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_ABGR32, + .mdp_color =3D MDP_COLOR_BGRA8888, + .depth =3D { 32 }, + .row_depth =3D { 32 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_ARGB32, + .mdp_color =3D MDP_COLOR_ARGB8888, + .depth =3D { 32 }, + .row_depth =3D { 32 }, + .num_planes =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_UYVY, + .mdp_color =3D MDP_COLOR_UYVY, + .depth =3D { 16 }, + .row_depth =3D { 16 }, + .num_planes =3D 1, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_VYUY, + .mdp_color =3D MDP_COLOR_VYUY, + .depth =3D { 16 }, + .row_depth =3D { 16 }, + .num_planes =3D 1, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YUYV, + .mdp_color =3D MDP_COLOR_YUYV, + .depth =3D { 16 }, + .row_depth =3D { 16 }, + .num_planes =3D 1, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YVYU, + .mdp_color =3D MDP_COLOR_YVYU, + .depth =3D { 16 }, + .row_depth =3D { 16 }, + .num_planes =3D 1, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YUV420, + .mdp_color =3D MDP_COLOR_I420, + .depth =3D { 12 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YVU420, + .mdp_color =3D MDP_COLOR_YV12, + .depth =3D { 12 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV12, + .mdp_color =3D MDP_COLOR_NV12, + .depth =3D { 12 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV21, + .mdp_color =3D MDP_COLOR_NV21, + .depth =3D { 12 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV16, + .mdp_color =3D MDP_COLOR_NV16, + .depth =3D { 16 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV61, + .mdp_color =3D MDP_COLOR_NV61, + .depth =3D { 16 }, + .row_depth =3D { 8 }, + .num_planes =3D 1, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV12M, + .mdp_color =3D MDP_COLOR_NV12, + .depth =3D { 8, 4 }, + .row_depth =3D { 8, 8 }, + .num_planes =3D 2, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_MM21, + .mdp_color =3D MDP_COLOR_420_BLK, + .depth =3D { 8, 4 }, + .row_depth =3D { 8, 8 }, + .num_planes =3D 2, + .walign =3D 6, + .halign =3D 6, + .flags =3D MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV21M, + .mdp_color =3D MDP_COLOR_NV21, + .depth =3D { 8, 4 }, + .row_depth =3D { 8, 8 }, + .num_planes =3D 2, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV16M, + .mdp_color =3D MDP_COLOR_NV16, + .depth =3D { 8, 8 }, + .row_depth =3D { 8, 8 }, + .num_planes =3D 2, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_NV61M, + .mdp_color =3D MDP_COLOR_NV61, + .depth =3D { 8, 8 }, + .row_depth =3D { 8, 8 }, + .num_planes =3D 2, + .walign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YUV420M, + .mdp_color =3D MDP_COLOR_I420, + .depth =3D { 8, 2, 2 }, + .row_depth =3D { 8, 4, 4 }, + .num_planes =3D 3, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YVU420M, + .mdp_color =3D MDP_COLOR_YV12, + .depth =3D { 8, 2, 2 }, + .row_depth =3D { 8, 4, 4 }, + .num_planes =3D 3, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YUV422M, + .mdp_color =3D MDP_COLOR_I422, + .depth =3D { 8, 4, 4 }, + .row_depth =3D { 8, 4, 4 }, + .num_planes =3D 3, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat =3D V4L2_PIX_FMT_YVU422M, + .mdp_color =3D MDP_COLOR_YV16, + .depth =3D { 8, 4, 4 }, + .row_depth =3D { 8, 4, 4 }, + .num_planes =3D 3, + .walign =3D 1, + .halign =3D 1, + .flags =3D MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + } +}; + static const struct mdp_limit mt8183_mdp_def_limit =3D { .out_limit =3D { .wmin =3D 16, @@ -403,6 +1020,25 @@ static const struct mdp_limit mt8183_mdp_def_limit = =3D { .v_scale_down_max =3D 128, }; =20 +static const struct mdp_limit mt8195_mdp_def_limit =3D { + .out_limit =3D { + .wmin =3D 64, + .hmin =3D 64, + .wmax =3D 8192, + .hmax =3D 8192, + }, + .cap_limit =3D { + .wmin =3D 64, + .hmin =3D 64, + .wmax =3D 8192, + .hmax =3D 8192, + }, + .h_scale_up_max =3D 64, + .v_scale_up_max =3D 64, + .h_scale_down_max =3D 128, + .v_scale_down_max =3D 128, +}; + static const struct mdp_pipe_info mt8183_pipe_info[] =3D { [MDP_PIPE_WPEI] =3D {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0}, [MDP_PIPE_WPEI2] =3D {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1}, @@ -410,6 +1046,20 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = =3D { [MDP_PIPE_RDMA0] =3D {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3} }; =20 +static const struct mdp_pipe_info mt8195_pipe_info[] =3D { + [MDP_PIPE_WPEI] =3D {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0}, + [MDP_PIPE_WPEI2] =3D {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1}, + [MDP_PIPE_IMGI] =3D {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2}, + [MDP_PIPE_RDMA0] =3D {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3}, + [MDP_PIPE_RDMA1] =3D {MDP_PIPE_RDMA1, MDP_MM_SUBSYS_1, 0}, + [MDP_PIPE_RDMA2] =3D {MDP_PIPE_RDMA2, MDP_MM_SUBSYS_1, 1}, + [MDP_PIPE_RDMA3] =3D {MDP_PIPE_RDMA3, MDP_MM_SUBSYS_1, 2}, + [MDP_PIPE_SPLIT] =3D {MDP_PIPE_SPLIT, MDP_MM_SUBSYS_1, 3}, + [MDP_PIPE_SPLIT2] =3D {MDP_PIPE_SPLIT2, MDP_MM_SUBSYS_1, 4}, + [MDP_PIPE_VPP1_SOUT] =3D {MDP_PIPE_VPP1_SOUT, MDP_MM_SUBSYS_0, 4}, + [MDP_PIPE_VPP0_SOUT] =3D {MDP_PIPE_VPP0_SOUT, MDP_MM_SUBSYS_1, 5}, +}; + const struct mtk_mdp_driver_data mt8183_mdp_driver_data =3D { .mdp_plat_id =3D MT8183, .mdp_con_res =3D 0x14001000, @@ -426,6 +1076,22 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_da= ta =3D { .pipe_info_len =3D ARRAY_SIZE(mt8183_pipe_info), }; =20 +const struct mtk_mdp_driver_data mt8195_mdp_driver_data =3D { + .mdp_plat_id =3D MT8195, + .mdp_con_res =3D 0x14001000, + .mdp_probe_infra =3D mt8195_mdp_probe_infra, + .mdp_sub_comp_dt_ids =3D mt8195_sub_comp_dt_ids, + .mdp_cfg =3D &mt8195_plat_cfg, + .mdp_mutex_table_idx =3D mt8195_mutex_idx, + .comp_data =3D mt8195_mdp_comp_data, + .comp_data_len =3D ARRAY_SIZE(mt8195_mdp_comp_data), + .format =3D mt8195_formats, + .format_len =3D ARRAY_SIZE(mt8195_formats), + .def_limit =3D &mt8195_mdp_def_limit, + .pipe_info =3D mt8195_pipe_info, + .pipe_info_len =3D ARRAY_SIZE(mt8195_pipe_info), +}; + s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) { if (!mdp_dev) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h b/drivers/m= edia/platform/mediatek/mdp3/mtk-img-ipi.h index 22b8b9a10ef7..08fb0853bcd5 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h @@ -115,6 +115,7 @@ struct img_frameparam { =20 /* Platform config indicator */ #define MT8183 8183 +#define MT8195 8195 =20 #define CFG_CHECK(plat, p_id) ((plat) =3D=3D (p_id)) =20 diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h b/drivers/= media/platform/mediatek/mdp3/mtk-mdp3-cfg.h index dfffc72868e4..49cdf45f6e59 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h @@ -10,6 +10,7 @@ #include =20 extern const struct mtk_mdp_driver_data mt8183_mdp_driver_data; +extern const struct mtk_mdp_driver_data mt8195_mdp_driver_data; =20 struct mdp_dev; enum mtk_mdp_comp_id; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-comp.c index e97630b7867c..600fec7d2f7f 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -773,6 +773,42 @@ static const struct of_device_id mdp_comp_dt_ids[] __m= aybe_unused =3D { }, { .compatible =3D "mediatek,mt8183-mdp3-wdma", .data =3D (void *)MDP_COMP_TYPE_WDMA, + }, { + .compatible =3D "mediatek,mt8195-mdp3-rdma", + .data =3D (void *)MDP_COMP_TYPE_RDMA, + }, { + .compatible =3D "mediatek,mt8195-mdp3-split", + .data =3D (void *)MDP_COMP_TYPE_SPLIT, + }, { + .compatible =3D "mediatek,mt8195-mdp3-stitch", + .data =3D (void *)MDP_COMP_TYPE_STITCH, + }, { + .compatible =3D "mediatek,mt8195-mdp3-fg", + .data =3D (void *)MDP_COMP_TYPE_FG, + }, { + .compatible =3D "mediatek,mt8195-mdp3-hdr", + .data =3D (void *)MDP_COMP_TYPE_HDR, + }, { + .compatible =3D "mediatek,mt8195-mdp3-aal", + .data =3D (void *)MDP_COMP_TYPE_AAL, + }, { + .compatible =3D "mediatek,mt8195-mdp3-merge", + .data =3D (void *)MDP_COMP_TYPE_MERGE, + }, { + .compatible =3D "mediatek,mt8195-mdp3-tdshp", + .data =3D (void *)MDP_COMP_TYPE_TDSHP, + }, { + .compatible =3D "mediatek,mt8195-mdp3-color", + .data =3D (void *)MDP_COMP_TYPE_COLOR, + }, { + .compatible =3D "mediatek,mt8195-mdp3-ovl", + .data =3D (void *)MDP_COMP_TYPE_OVL, + }, { + .compatible =3D "mediatek,mt8195-mdp3-padding", + .data =3D (void *)MDP_COMP_TYPE_PAD, + }, { + .compatible =3D "mediatek,mt8195-mdp3-tcc", + .data =3D (void *)MDP_COMP_TYPE_TCC, }, {} }; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-core.c index 6ddb5e075f5d..a6c71fd9e5bf 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -21,6 +21,12 @@ static const struct of_device_id mdp_of_ids[] =3D { { .compatible =3D "mediatek,mt8183-mdp3-rdma", .data =3D &mt8183_mdp_driver_data, }, + { .compatible =3D "mediatek,mt8195-mdp3-rdma", + .data =3D &mt8195_mdp_driver_data, + }, + { .compatible =3D "mediatek,mt8195-mdp3-wrot", + .data =3D &mt8195_mdp_driver_data, + }, {}, }; MODULE_DEVICE_TABLE(of, mdp_of_ids); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-core.h index e57c415a1c78..d6484d17b09f 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -49,10 +49,16 @@ struct mdp_platform_config { bool rdma_support_10bit; bool rdma_rsz1_sram_sharing; bool rdma_upsample_repeat_only; + bool rdma_esl_setting; u32 rdma_event_num; bool rsz_disable_dcm_small_sample; + bool rsz_etc_control; bool wrot_filter_constraint; + bool wrot_support_10bit; u32 wrot_event_num; + u32 tdshp_hist_num; + bool tdshp_constrain; + bool tdshp_contour; }; =20 /* indicate which mutex is used by each pipepline */ --=20 2.18.0