From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 311C7210E7; Wed, 20 Dec 2023 10:09:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="A4fNBGwd" X-UUID: c95aeaec9f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=E8/fAekjxBykSa2BC/K/wB1RyxJ+T73gazGdt8LU+ro=; b=A4fNBGwdar4b21kjy94l0rGRV5JBawbAtxu+qYYISSbEMAtBF6p1/g8Qd3eLzMmDJGwIwKFBckghqxNbrVnywMv1q4/Hp0EWqeYKaEYHOhNHyUo7th/Hr52UYzEOcEPW6XlaZVGqIXKDFqpyYkWkw8l7tyYYI5slBiW3Q4XMBSc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:182ceb15-f65b-4ddc-8a23-bc0f11e42a3b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:755d618d-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c95aeaec9f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 336852908; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:54 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v10 01/16] dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with generic names Date: Wed, 20 Dec 2023 18:08:38 +0800 Message-ID: <20231220100853.20616-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.069300-8.000000 X-TMASE-MatchedRID: xwCqL1bJw75eJRw5hj8/hCZm6wdY+F8KvtVce6w5+K8QHQ+7AkbTsXGp r8/fPJWivQEW+BqnrVrnftxNodBrx8RBLZ5x+SkXH5YQyOg71ZYW40XiUkbrG9zOQo7mTgA+gT4 HLsARG1siA7lT3EYqXMCl/H6TvsoyfyoI97TEvxDdQFsmvD2aF30tCKdnhB589yM15V5aWpj6C0 ePs7A07fhmFHnZFzVq1OS3M18QrJopR/2mSzr5VUVwkBGNaI1zumB3z3Qn489PLuriof24z8mh2 Ib2qzHYNwVlEe2OlsJhNCbU2IFr3KM+tI+Th6+NSZrfNhP3sgUBh9AgBSEFrJm+YJspVvj2xkvr HlT8euJ0YHKn7N1oOA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.069300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7079FCC34D3987DC402CD37B3F603F7FC627810880967878C43FCEF9CFEEA3DD2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names. In addition, fix improper space indent in example. Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTe= k MDP3 components") Signed-off-by: Moudy Ho Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,mdp3-rdma.yaml | 29 +++++++++++-------- .../bindings/media/mediatek,mdp3-wrot.yaml | 23 +++++++++------ 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index 59dcea797b71..e1ffe7eb2cdf 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -69,6 +69,9 @@ properties: - description: used for 1st data pipe from RDMA - description: used for 2nd data pipe from RDMA =20 + '#dma-cells': + const: 1 + required: - compatible - reg @@ -78,6 +81,7 @@ required: - clocks - iommus - mboxes + - '#dma-cells' =20 additionalProperties: false =20 @@ -88,16 +92,17 @@ examples: #include #include =20 - mdp3_rdma0: mdp3-rdma0@14001000 { - compatible =3D "mediatek,mt8183-mdp3-rdma"; - reg =3D <0x14001000 0x1000>; - mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; - mediatek,gce-events =3D , - ; - power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; - clocks =3D <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MDP_RSZ1>; - iommus =3D <&iommu>; - mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST>, - <&gce 21 CMDQ_THR_PRIO_LOWEST>; + dma-controller@14001000 { + compatible =3D "mediatek,mt8183-mdp3-rdma"; + reg =3D <0x14001000 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus =3D <&iommu>; + mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>; + #dma-cells =3D <1>; }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 0baa77198fa2..64ea98aa0592 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -50,6 +50,9 @@ properties: iommus: maxItems: 1 =20 + '#dma-cells': + const: 1 + required: - compatible - reg @@ -58,6 +61,7 @@ required: - power-domains - clocks - iommus + - '#dma-cells' =20 additionalProperties: false =20 @@ -68,13 +72,14 @@ examples: #include #include =20 - mdp3_wrot0: mdp3-wrot0@14005000 { - compatible =3D "mediatek,mt8183-mdp3-wrot"; - reg =3D <0x14005000 0x1000>; - mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; - mediatek,gce-events =3D , - ; - power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; - clocks =3D <&mmsys CLK_MM_MDP_WROT0>; - iommus =3D <&iommu>; + dma-controller@14005000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0x14005000 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_WROT0>; + iommus =3D <&iommu>; + #dma-cells =3D <1>; }; --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4805A2231C; Wed, 20 Dec 2023 10:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="A4sbYqYM" X-UUID: c96d351c9f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3E3oH9it2snq+feJmOtJhpPs4tSb7On1BA+4yh3+JIQ=; b=A4sbYqYMTrLIIzNEA16NLCfYSrmEtRv0yGJMSzoMNV7c1flqXE5wt8CpE+aiBoT67SYGKOfWz3QbpBBsplBD+FYcfe2Lei2O+13vPNlqSEmODWtjaxcB91mpSqvGwnIYgXUA4hS3Jplw3jVpqRR9GoFkbhNeptKKZZnUnlzQYJc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:78fcc428-4b3b-4b23-a993-3d12d4e4b312,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:49c64b2e-1ab8-4133-9780-81938111c800,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c96d351c9f1f11eeba30773df0976c77-20231220 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 114935694; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v10 02/16] dt-bindings: media: mediatek: mdp3: merge the indentical RDMA under display Date: Wed, 20 Dec 2023 18:08:39 +0800 Message-ID: <20231220100853.20616-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--10.633600-8.000000 X-TMASE-MatchedRID: /qtm/HvCCyP6W4x/FkbM/rg7LINv5Afgh8Ytn75ClDN03GAz54To+1jt prj9/vncN+HT16szfKKIJs0Up7vkWEHeh2kdZPDc7spMO3HwKCAW40XiUkbrG/EJBoK3pfxuECM 3iFpuDiiHPPuXAmrjKSvG+CY9d4AKupptyy2mu+7iHyvyXeXh5m3eqxoVjgMEqiVpIcIW6utWPf j/g9xP8xaxmhrgB4zxR7wbWUwlw6pOFGkXM6YcX8nUT+eskUQPgRykyfrH1xlaW2Ktn+I8/vz8v ajouc6XpDfNjU0xuVbMDVOmx+2sBkBduJGafVsPCz1WR8KHe4AT28gbcGU2vaMwbOPeRq+ao8WM kQWv6iVfx6Zf83Do5eTCMddcL/gjymsk/wUE4hoV2mQ/HE5Pbkp3yNYGG3owwXF5Ugr5BMd2zec STLTuipluOY2svJYY X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--10.633600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A62A3C849CBA1F6BFEF2121248B0758E7E2273D00DCB3560D322FBABFFB364992000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To simplify maintenance and avoid branches, the identical component should be merged and placed in the path belonging to the MDP (from display/* to media/*). In addition, currently only MDP utilizes RDMA through CMDQ, and the necessary properties for "mediatek,gce-events", and "mboxes" have been set up for this purpose. Within DISP, it directly receives component interrupt signals. Signed-off-by: Moudy Ho --- .../display/mediatek/mediatek,mdp-rdma.yaml | 92 ------------------- .../bindings/media/mediatek,mdp3-rdma.yaml | 43 ++++++++- 2 files changed, 40 insertions(+), 95 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,mdp-rdma.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,md= p-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,m= dp-rdma.yaml deleted file mode 100644 index 7570a0684967..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.= yaml +++ /dev/null @@ -1,92 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek MDP RDMA - -maintainers: - - Chun-Kuang Hu - - Philipp Zabel - -description: - The MediaTek MDP RDMA stands for Read Direct Memory Access. - It provides real time data to the back-end panel driver, such as DSI, - DPI and DP_INTF. - It contains one line buffer to store the sufficient pixel data. - RDMA device node must be siblings to the central MMSYS_CONFIG node. - For a description of the MMSYS_CONFIG binding, see - Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for d= etails. - -properties: - compatible: - oneOf: - - const: mediatek,mt8195-vdo1-rdma - - items: - - const: mediatek,mt8188-vdo1-rdma - - const: mediatek,mt8195-vdo1-rdma - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - clocks: - items: - - description: RDMA Clock - - iommus: - maxItems: 1 - - mediatek,gce-client-reg: - description: - The register of display function block to be set by gce. There are 4= arguments, - such as gce node, subsys id, offset and register size. The subsys id= that is - mapping to the register of display function blocks is defined in the= gce header - include/dt-bindings/gce/-gce.h of each chips. - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - items: - - description: phandle of GCE - - description: GCE subsys id - - description: register offset - - description: register size - maxItems: 1 - -required: - - compatible - - reg - - power-domains - - clocks - - iommus - - mediatek,gce-client-reg - -additionalProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - - rdma@1c104000 { - compatible =3D "mediatek,mt8195-vdo1-rdma"; - reg =3D <0 0x1c104000 0 0x1000>; - interrupts =3D ; - clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; - power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; - mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x4000 0x10= 00>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index e1ffe7eb2cdf..e9955639ce19 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -20,8 +20,12 @@ description: | =20 properties: compatible: - items: + oneOf: - const: mediatek,mt8183-mdp3-rdma + - const: mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma =20 reg: maxItems: 1 @@ -60,6 +64,7 @@ properties: items: - description: RDMA clock - description: RSZ clock + minItems: 1 =20 iommus: maxItems: 1 @@ -68,6 +73,10 @@ properties: items: - description: used for 1st data pipe from RDMA - description: used for 2nd data pipe from RDMA + minItems: 1 + + interrupts: + maxItems: 1 =20 '#dma-cells': const: 1 @@ -76,13 +85,41 @@ required: - compatible - reg - mediatek,gce-client-reg - - mediatek,gce-events - power-domains - clocks - iommus - - mboxes - '#dma-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-mdp3-rdma + + then: + properties: + clocks: + minItems: 2 + + mboxes: + minItems: 2 + + required: + - mboxes + - mediatek,gce-events + + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-vdo1-rdma + + then: + properties: + clocks: + maxItems: 1 + additionalProperties: false =20 examples: --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A49D25558; Wed, 20 Dec 2023 10:09:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="haMzCh1D" X-UUID: c93d20b69f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mhfk3FqNlNnTIC11+3AiswpDac8u08Q0N1jKnCvU8fs=; b=haMzCh1DObPNY0aHo4JfO1Z6rkMKdflNUIEXNkEOfzyrl5soMjCYt+2CCznyMtLkRTqfM9dwQDNuw5vt9qsku+qufYXdPRjVUgnPkEhWX/HZlr1tfmA5e1IynOgYbxpmsPaW5N9OOAV74Mhp/O7NOyDY6hniMi6RtPzMFDUoxCE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:ad449947-0f06-4010-9291-b28356eeca9f,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:5d391d7,CLOUDID:9a537a7e-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,D KR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c93d20b69f1f11eeba30773df0976c77-20231220 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1364811328; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 03/16] dt-bindings: media: mediatek: mdp3: add config for MT8195 RDMA Date: Wed, 20 Dec 2023 18:08:40 +0800 Message-ID: <20231220100853.20616-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Added the configuration for MT8195 RDMA. In comparison to MT8183, it no longer shares SRAM with RSZ, and there are now preconfigured 5 mbox. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring --- .../bindings/media/mediatek,mdp3-rdma.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index e9955639ce19..f9ca66413d51 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -22,6 +22,7 @@ properties: compatible: oneOf: - const: mediatek,mt8183-mdp3-rdma + - const: mediatek,mt8195-mdp3-rdma - const: mediatek,mt8195-vdo1-rdma - items: - const: mediatek,mt8188-vdo1-rdma @@ -73,6 +74,9 @@ properties: items: - description: used for 1st data pipe from RDMA - description: used for 2nd data pipe from RDMA + - description: used for 3rd data pipe from RDMA + - description: used for 4th data pipe from RDMA + - description: used for the data pipe from SPLIT minItems: 1 =20 interrupts: @@ -109,6 +113,23 @@ allOf: - mboxes - mediatek,gce-events =20 + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-rdma + + then: + properties: + clocks: + maxItems: 1 + + mboxes: + minItems: 5 + + required: + - mediatek,gce-events + - if: properties: compatible: --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9C5621356; Wed, 20 Dec 2023 10:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="X+dhMEfp" X-UUID: c8fd59409f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GuaatKpJJKQ8P3UzwE+5PZkOWfDZVusyH/8yORVTn1k=; b=X+dhMEfp0S5OrRvH+xbssiNyYnjK5qS5xcad2g2YcMnheQ0bzssrvRYX8UrtZEJch4JefDZateku+viF8Y6EuORSG2soEGeqfPk0PsmQhxa9y7brmgUBS8nCYs3i124dZO8RseK8YnHrm189cDofLGgWG/7dXOvOB1SDxpVQPYU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:599d3610-eab4-4924-8714-46b156c559d3,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:99537a7e-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c8fd59409f1f11eeba30773df0976c77-20231220 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 314757466; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 04/16] dt-bindings: media: mediatek: mdp3: add compatible for MT8195 RSZ Date: Wed, 20 Dec 2023 18:08:41 +0800 Message-ID: <20231220100853.20616-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8195 RSZ inherited from MT8183, add the corresponding compatible name to it. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/media/mediatek,mdp3-rsz.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml= b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index 78f9de6192ef..f5676bec4326 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -15,9 +15,13 @@ description: | =20 properties: compatible: - items: + oneOf: - enum: - mediatek,mt8183-mdp3-rsz + - items: + - enum: + - mediatek,mt8195-mdp3-rsz + - const: mediatek,mt8183-mdp3-rsz =20 reg: maxItems: 1 --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F39210E5; Wed, 20 Dec 2023 10:09:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HN9tVu73" X-UUID: c901860a9f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Vb24kkSmzFqLkYt275IGRO8kfWGasUiCdUh0M9mkibA=; b=HN9tVu73nph1XIrN5v4vcZ/csfFUxCRvjRqQ4Pe6Pu0eXHZmxkxcn/RtP27zWBPlyIUxOXT6h1fLJxi4hZ2F3U+6rehYYSejp8updZo5HYkjLKqXT89NMw3XfyWMsPYu8JFGPpmQr1HBsgmhLE/oIIV+fUdHrr97X9PoMhk/LfE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:245400d5-d759-4e9e-98cb-d2d815148f39,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:725d618d-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c901860a9f1f11eeba30773df0976c77-20231220 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 168523288; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 05/16] dt-bindings: media: mediatek: mdp3: add compatible for MT8195 WROT Date: Wed, 20 Dec 2023 18:08:42 +0800 Message-ID: <20231220100853.20616-6-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8195 WROT inherited from MT8183, add the corresponding compatible name to it. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/media/mediatek,mdp3-wrot.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 64ea98aa0592..53a679338402 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -15,9 +15,13 @@ description: | =20 properties: compatible: - items: + oneOf: - enum: - mediatek,mt8183-mdp3-wrot + - items: + - enum: + - mediatek,mt8195-mdp3-wrot + - const: mediatek,mt8183-mdp3-wrot =20 reg: maxItems: 1 --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49032208C8; Wed, 20 Dec 2023 10:09:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="TumoAhe/" X-UUID: c9056fe09f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ZbKsTEXQ06nZKi8eEHm/YLTPz1FZJoAUmXN9IUI475U=; b=TumoAhe/2tbsmE5lsLyC16m9fk5HoaFOmdRajhpiFXjmFaxF438JbYYElfUbJ5Tw2MfFl/poaXfOhtKRCDEzvgDjCJcfD5GzHZZ06+ALTXrKw4Z9j3tPFI0Q9VSCDUPld68nNBerEapSvfxwWBjAqSr9GXDo79mXmRJNbRKTRuU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:442cc47a-c99c-4970-bc15-77e14671194b,IP:0,U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:5d391d7,CLOUDID:48c64b2e-1ab8-4133-9780-81938111c800,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c9056fe09f1f11eeba30773df0976c77-20231220 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 398409639; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 06/16] dt-bindings: media: mediatek: mdp3: add component FG for MT8195 Date: Wed, 20 Dec 2023 18:08:43 +0800 Message-ID: <20231220100853.20616-7-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the fundamental hardware configuration of component FG, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-fg.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-f= g.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml = b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml new file mode 100644 index 000000000000..03f31b009085 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Film Grain + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + Film Grain (FG) is a Media Data Path 3 (MDP3) component used to add + the film grain according to the AOMedia Video 1 (AV1) standard. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-fg + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14002000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0x14002000 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_FG>; + }; --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27873210E6; Wed, 20 Dec 2023 10:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lo7dK8+J" X-UUID: c98ed2da9f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8l5B9d28IzVrTNFOgQusSXRsLqIIUpnduD1x+ROUPPw=; b=lo7dK8+JfNc24QCOEezS37OkvYGKlrBiV14vrY6Vefu/6zXpJFcUaZWippYSwVyA1gLArFfhhi6rSMmCCOPpCgd18diTF0nZtEdz7SdZQNjMR/szlbh0fXa2doyZ/GFd751IEs7v9vHaPCe8QZaBQIAc1mUPl7yHhYQcZyguQUY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:acca5712-b61e-4fc3-be61-90cede373e17,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5d391d7,CLOUDID:745d618d-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c98ed2da9f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 230330188; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 07/16] dt-bindings: media: mediatek: mdp3: add component HDR for MT8195 Date: Wed, 20 Dec 2023 18:08:44 +0800 Message-ID: <20231220100853.20616-8-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the fundamental hardware configuration of component HDR, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-hdr.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-h= dr.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml= b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml new file mode 100644 index 000000000000..d4609bba6578 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 HDR + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + A Media Data Path 3 (MDP3) component used to perform conversion from + High Dynamic Range (HDR) to Standard Dynamic Range (SDR). + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-hdr + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14004000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0x14004000 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_HDR>; + }; --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AF72210E4; Wed, 20 Dec 2023 10:08:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="nJquP7Tv" X-UUID: c991934e9f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ryL3xIPJfg8A+byFMnd2zFxavybUfKzdvdWAdO/yaJo=; b=nJquP7TvYYot3MdOdZZI2mngj2ET8VJiz5jxwG+QKEemNHIJdOhuVhfb85ttmHposySf5V2x6mjmUJMkLHeTh/fxv65z3Njk0M3CGub+IAJtrEqTLfPJe1LpYpjp0gA3YBhWIev/wbuZaQyw5T6LPcBXmxKTxSeL5xsV/hNC5d4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:ffbf317f-3d71-47f4-ab0d-1cb825b3fe80,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5d391d7,CLOUDID:9e537a7e-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c991934e9f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 892679969; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:55 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 08/16] dt-bindings: media: mediatek: mdp3: add component STITCH for MT8195 Date: Wed, 20 Dec 2023 18:08:45 +0800 Message-ID: <20231220100853.20616-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the fundamental hardware configuration of component STITCH, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,mdp3-stitch.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-s= titch.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.y= aml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml new file mode 100644 index 000000000000..d815bea29154 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 STITCH + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + One of Media Data Path 3 (MDP3) components used to combine multiple vide= o frame + with overlapping fields of view to produce a segmented panorame. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-stitch + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14003000 { + compatible =3D "mediatek,mt8195-mdp3-stitch"; + reg =3D <0x14003000 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_STITCH>; + }; --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37750374DA; Wed, 20 Dec 2023 10:09:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qkSlkt3M" X-UUID: ca675fa69f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5QjcwvzrebWfLqJww9KhwNbe3Z1/pLAvIef2nvvVTbQ=; b=qkSlkt3MtEjWc7Ki2wH8SrK6Yo2WXqgFPwz5Ntn5F4Oq6oD5ktUwSp7P0l/N9ak6na+FudaSlIVnufEy8iPgxGrYsZX5Oe0WDz2NMsSpH2pvRf2pOBwUnlDubyLsr2kPEk7SFsGRe9veFOyxK2KBZZ/5XdvJVqyGZNWMja3uu94=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:3ec8e272-191a-40a4-9f41-26606105510c,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5d391d7,CLOUDID:5bc64b2e-1ab8-4133-9780-81938111c800,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: ca675fa69f1f11eeba30773df0976c77-20231220 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1404044826; Wed, 20 Dec 2023 18:08:58 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:56 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v10 09/16] dt-bindings: media: mediatek: mdp3: add component TCC for MT8195 Date: Wed, 20 Dec 2023 18:08:46 +0800 Message-ID: <20231220100853.20616-10-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.626500-8.000000 X-TMASE-MatchedRID: mSPDr4jZDFHoRPKKjGHPUxcqpH7D1rtQ6SXuwUgGH0j3dSKTMI31W4pb wG9fIuITLSHDQi/tZU+OEmLXxEuoAga1NXbjqus0tw+xHnsmQjNr9+Kgn2XgeNzOQo7mTgA+apc xcfGIwwyygic1mDySMHMPxAree1voSBiSH4+du3/J1E/nrJFED4EcpMn6x9cZWltirZ/iPP78/L 2o6LnOl6Q3zY1NMblWzA1TpsftrAZAXbiRmn1bD54CIKY/Hg3Am4n49vyf9XEvM/mydp5vVCq2r l3dzGQ1ropAi/FV10zL1e8sURC8p7/zMsx+tBCWzRJ7qMxdWrq5TR54AAUwADflzkGcoK72 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.626500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7C91E7E3977F679A768A5E78CC02B31B3EC1C9BBB412000CA196C164DECA461A2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the fundamental hardware configuration of component TCC, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-t= cc.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml= b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml new file mode 100644 index 000000000000..14ea556d4f82 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Tone Curve Conversion + +maintainers: + - Matthias Brugger + +description: + Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) compon= ents. + It is used to handle the tone mapping of various gamma curves in order to + achieve HDR10 effects. This helps adapt the content to the color and + brightness range that standard display devices typically support. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tcc + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@1400b000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0x1400b000 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TCC>; + }; --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CED7724B29; Wed, 20 Dec 2023 10:09:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Pxlq2Zl8" X-UUID: ca6b76ea9f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Ma17REYBRtjPcEsPfc2uYW9/mewROjVPdPZMaWhYQoA=; b=Pxlq2Zl8TmNl7WTPi9hZ2wDfzLTdLf0R2BBgkNTHEJ/lPK1tK9wuslM0VYaIrNjLboG3+/7jYTzLCitGTehHsjhIOIGhiCMqpSzKfaC4qRjbL+7HZ2qum2UR1NuPCP7a8JeYGeuWeHqN7RYICB7otS/1x/xCDN9S2OW/eszZKTA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:e25e5b4e-0faf-452a-a013-949a20facb99,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5d391d7,CLOUDID:4f7cfa81-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: ca6b76ea9f1f11eeba30773df0976c77-20231220 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 756042144; Wed, 20 Dec 2023 18:08:58 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:56 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v10 10/16] dt-bindings: media: mediatek: mdp3: add component TDSHP for MT8195 Date: Wed, 20 Dec 2023 18:08:47 +0800 Message-ID: <20231220100853.20616-11-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.393800-8.000000 X-TMASE-MatchedRID: WbOLpgv9C7boRPKKjGHPUxcqpH7D1rtQ6SXuwUgGH0j3dSKTMI31W4pb wG9fIuITLSHDQi/tZU+OEmLXxEuoAga1NXbjqus0tw+xHnsmQjNr9+Kgn2XgeNzOQo7mTgA+Suc qLHu3mZN3IL9RTZjcZXNjxEfTH8yUnuh7s4XRTZbBVprK8rvWX3+vzHfC29pfzsQ8iRVyD45ZoZ UwtnkREuLzNWBegCW2U9w4XVXDWCYLbigRnpKlKTpcQTtiHDgWYMtEQ3cbds7Ei+qbBd9QrMmH1 /XL/GC7MpyARfAv4kgvNzC4CXWKgUMMprcbiest X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.393800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B55B01B7F8A6687577BF07219B6DD270A6B3F6B7A00ED7E37F6FCB0E0375745D2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the fundamental hardware configuration of component TDSHP, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-t= dshp.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.ya= ml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml new file mode 100644 index 000000000000..8ab7f2d8e148 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Two-Dimensional Sharpness + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) compo= nent + used to perform image edge sharpening and enhance vividness and contrast. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tdshp + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14007000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0x14007000 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46AE421109; Wed, 20 Dec 2023 10:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="AqDAZA1N" X-UUID: ca22b57c9f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uBjiNYTO2WSmvyy9DZRC1WiD40IMo3yDRg/HtSKYR6I=; b=AqDAZA1NiHDDZxbmjYrfvK2I8nr+4ctQPpQfQETQEDS3zTWlkHohYb+smuv4d6XJPX+MFPWYbIdrsKV0SlgWGNEcvwH+1++emYIsU6scT8yOjstPaEQRE15uC7Z4/vDwqC69NfmJL1PsEdGXCtJ3cN1xCAGI3gcy/XosxZ4Y/OA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:aa5d191e-8d67-46c4-a842-0697af7f3fc3,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:567cfa81-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca22b57c9f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1763914329; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:56 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v10 11/16] dt-bindings: display: mediatek: aal: add compatible for MT8195 Date: Wed, 20 Dec 2023 18:08:48 +0800 Message-ID: <20231220100853.20616-12-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.516100-8.000000 X-TMASE-MatchedRID: tiRXYRqWr+smeoNhEXvE7GNW0DAjL5p++OI6XsK3BWHfUZT83lbkEA0F DzFL1GEo4vM1YF6AJbbGJQ3BiiLAggtuKBGekqUpOlxBO2IcOBaO/ztVD2SNfpCcms+5v4uXzy8 6IVrD8hgOwdiW90VdamUJHNwT58zWNku6yeuF7hhnLOYoxSKnYyv7g0tvDN5nt7OOvAvgUMHBkG BTIlURuXoXDz8+lMxFpW+aIDJ4DaRzkxJ+SIkUjlAEm1wpw5h+lExlQIQeRG0= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.516100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 5F02470A2F91E359BD13355918A4CF1201C577976DDAC37EE2D83F5BE0E200792000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for the AAL block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aa= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.ya= ml index 7fd42c8fdc32..b4c28e96dd55 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59BC220B0C; Wed, 20 Dec 2023 10:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jtAbogP1" X-UUID: ca082e329f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=S+BFsscpOYXgIjZ4vvUEbFaZKileuAcJkmvyZC22tyQ=; b=jtAbogP1CHA5RZKR/1xH8sJPpEETy/YRAzjNNwewZa/gr1X3aNwFUTbGi6fCoeHX4SkPWaN8kJvSziMpfiaj3ckSS+c2vMJKvBxsZ9aqd4M/fpfLKuLzbmx7iygrg2K7I5FYUKvf65K9hVGe3+GVk8D3aDxt+pJSLo5dd9fQ2gI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:3c043129-4616-4128-b952-1f055fc1d20e,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:537cfa81-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca082e329f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1901286352; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:56 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 12/16] dt-bindings: display: mediatek: color: add compatible for MT8195 Date: Wed, 20 Dec 2023 18:08:49 +0800 Message-ID: <20231220100853.20616-13-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for the COLOR block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,co= lor.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,colo= r.yaml index f21e44092043..b886ca0d89ea 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-disp-color - mediatek,mt8167-disp-color - mediatek,mt8173-disp-color + - mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD5BC20DFA; Wed, 20 Dec 2023 10:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lpwjcdFM" X-UUID: ca211df29f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=7GscIB2L0dT+RKBtElRpAI2KEhzZqSKJ7wBRtBaZfo0=; b=lpwjcdFMJ4XCFkmuNjh/vBpIoioF6JVz3OL2uHQv6TEcN47lp9MgxrN3flRNnAs6YSgt7v6I+dfVaXtQDOY5KJJw5hJWNm5cG8YdeOo37Dq6SzPZ71InqCvDr5w/0czBsu+qQrxMxRC/LRPGuRLgeuRoAHoAfEDbwcLjcG/ApWg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:de23afb3-02d5-4d26-8c60-46d2cce08ae9,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:557cfa81-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca211df29f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 91567424; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:56 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 13/16] dt-bindings: display: mediatek: merge: add compatible for MT8195 Date: Wed, 20 Dec 2023 18:08:50 +0800 Message-ID: <20231220100853.20616-14-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for the MERGE block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,me= rge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merg= e.yaml index 5c678695162e..dae839279950 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-merge - mediatek,mt8195-disp-merge + - mediatek,mt8195-mdp3-merge - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4494021108; Wed, 20 Dec 2023 10:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="G4uAAUnV" X-UUID: ca5de11a9f1f11eeba30773df0976c77-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CZfwX/wsWCkwVK0PMNBkW/bjKkWMLaDfZFL2RraVoKE=; b=G4uAAUnVkIhn0yRD0dmTlBu6dnuGOf6JlXJU8tKYoRU8qoWcTYGVZH4CUsF85WAf55RZNdq+5hQT8ia6btWfPeIGPj1R0RbHotdZfk+KrcwPSC0iW9PXjs6RuFN6ZWq965feHJq+0vkCcUs35YUWozSsUCl1xTAO/RQiRzBW6no=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:85f45529-2d20-4e2a-8dee-cc1d1089817c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:5ac64b2e-1ab8-4133-9780-81938111c800,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca5de11a9f1f11eeba30773df0976c77-20231220 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 635752283; Wed, 20 Dec 2023 18:08:58 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:56 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 14/16] dt-bindings: display: mediatek: ovl: add compatible for MT8195 Date: Wed, 20 Dec 2023 18:08:51 +0800 Message-ID: <20231220100853.20616-15-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for the OVL block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ov= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.ya= ml index 3e1069b00b56..c471a181d125 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl + - mediatek,mt8195-mdp3-ovl - items: - enum: - mediatek,mt7623-disp-ovl --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 410E221378; Wed, 20 Dec 2023 10:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tzsDckxi" X-UUID: ca2551ce9f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tJf5yBrmP9+h3QbyKaZHSTjQbagz9H0rJQiO4PcgBeM=; b=tzsDckxivlCoqe/6LBp/NJGpzGkucW2VQj47WSNxkbETMvdYsrLWeOBgBFPtl9QNEvD81RtY0xFfgkQdf6CMcUiMLisSxLexU6WDCI2Ns0RY4am00z74bYRUrv/8dzYMwUPuKwSAhclekw5t+wE009102/Gf9uiD2cYsIyG0P0c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:3540aef8-907b-4aad-884f-b83571c482ec,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:547cfa81-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca2551ce9f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1235464029; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:57 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v10 15/16] dt-bindings: display: mediatek: split: add compatible for MT8195 Date: Wed, 20 Dec 2023 18:08:52 +0800 Message-ID: <20231220100853.20616-16-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.601900-8.000000 X-TMASE-MatchedRID: iSQL5szRvdEmeoNhEXvE7GNW0DAjL5p++OI6XsK3BWHfUZT83lbkEItz U8iLelfKk5fnUPZTc0s2rGI383MBk6LCTO1UKypvSEQN/D/3cG6H7D1bP/FcOlmmz7LVVfOpZBw rIERGz+EZoBsQWiqLArpjAjMHHtZlHxPMjOKY7A8LbigRnpKlKTpcQTtiHDgW5Q+Bm+TIeXAeWq FdbyWvC5jmE9ANWG0Ol5kCTqXarhuP6/1EAjxJyV4Vqu1jjx3ewtvdkgBWssu8enuHvqOd7i18q lBVnRX0wZBgUyJVEbl6Fw8/PpTMRaVvmiAyeA2kc5MSfkiJFI5p3LlElBHTlw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.601900-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2C204B67FA4184FFB7BA7E558FD1464141EEFDFF9275A3FDC2BBEF0A63451AB92000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string and GCE property for MT8195 SPLIT, of which is operated by MDP3. Signed-off-by: Moudy Ho Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,split.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,sp= lit.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,spli= t.yaml index a8a5c9608598..e4affc854f3d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt8173-disp-split + - mediatek,mt8195-mdp3-split - items: - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split @@ -38,6 +39,21 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + clocks: items: - description: SPLIT Clock @@ -48,6 +64,17 @@ required: - power-domains - clocks =20 +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-split + + then: + required: + - mediatek,gce-client-reg + additionalProperties: false =20 examples: --=20 2.18.0 From nobody Sun Nov 10 07:02:12 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81C6820B18; Wed, 20 Dec 2023 10:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="mUy3sZW8" X-UUID: ca0ab7429f1f11eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=h5rIsp5+I+SkmadGTO7Dcz836VjuIt1iX+A2hptaRFs=; b=mUy3sZW8dY8geAhUYe2Zabobi+kPQnOHASMMPqNYLLwy6dxBOWYbV4v4U1szVlx6Ceib5M2oRdq3Dppj5ZKQdHThTS8y2jU+m53/Y7f96vGW/JOwpDxNHnYSB6jMeMb2l5rpVszKpmlQoJUhwt4OfV3HOGUtGyvvtv9ulgdSgY4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:2477c050-bc2a-49cf-839d-f366646a6ccc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:b5537a7e-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca0ab7429f1f11eea5db2bebc7c28f94-20231220 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 444357784; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:08:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:08:57 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v10 16/16] dt-bindings: display: mediatek: padding: add compatible for MT8195 Date: Wed, 20 Dec 2023 18:08:53 +0800 Message-ID: <20231220100853.20616-17-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220100853.20616-1-moudy.ho@mediatek.com> References: <20231220100853.20616-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for the PADDING block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/display/mediatek/mediatek,padding.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml index 6bad7dc2d69f..be07bbdc54e3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y= aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y= aml @@ -20,7 +20,9 @@ description: =20 properties: compatible: - const: mediatek,mt8188-disp-padding + enum: + - mediatek,mt8188-disp-padding + - mediatek,mt8195-mdp3-padding =20 reg: maxItems: 1 --=20 2.18.0