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[31.10.153.16]) by smtp.gmail.com with ESMTPSA id p7-20020a056402500700b0055283720ec3sm5979043eda.76.2023.12.19.23.38.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 23:38:11 -0800 (PST) From: Aleksandrs Vinarskis To: tiwai@suse.de Cc: alex.vinarskis@gmail.com, alsa-devel@alsa-project.org, david.rhodes@cirrus.com, james.schulman@cirrus.com, josbeir@gmail.com, linux-kernel@vger.kernel.org, patches@opensource.cirrus.com, perex@perex.cz, sbinding@opensource.cirrus.com, stuarth@opensource.cirrus.com, tiwai@suse.com Subject: [PATCH v2 1/2] ALSA: hda: cs35l41: Safety-guard against capped SPI speed Date: Wed, 20 Dec 2023 08:38:08 +0100 Message-Id: <20231220073809.22027-2-alex.vinarskis@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231220073809.22027-1-alex.vinarskis@gmail.com> References: <87ttokpyws.wl-tiwai@suse.de> <20231220073809.22027-1-alex.vinarskis@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some devices with intel-lpss based SPI controllers may have misconfigured clock divider due to firmware bug. This would result in capped SPI speeds, which leads to longer DSP firmware loading times. This safety guards against possible hangs during wake-up by not initializing the device if lpss was not patched/fixed UEFI was not installed Signed-off-by: Aleksandrs Vinarskis --- sound/pci/hda/cs35l41_hda_property.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda_property.c b/sound/pci/hda/cs35l41_h= da_property.c index c9eb70290973..cb305b093311 100644 --- a/sound/pci/hda/cs35l41_hda_property.c +++ b/sound/pci/hda/cs35l41_hda_property.c @@ -210,6 +210,19 @@ static int generic_dsd_config(struct cs35l41_hda *cs35= l41, struct device *physde =20 if (cfg->bus =3D=3D SPI) { cs35l41->index =3D id; + /* + * Some devices with intel-lpss based SPI controllers may have misconfig= ured + * clock divider due to firmware bug. This would result in capped SPI sp= eeds, + * which leads to longer DSP firmware loading times. + * Avoid initializing device if lpss was not patched/fixed UEFI was not = installed + */ + spi =3D to_spi_device(cs35l41->dev); + if (spi->max_speed_hz < CS35L41_SPI_MAX_FREQ/2) { + dev_err(cs35l41->dev, + "SPI's max_speed_hz is capped at %u Hz, will not continue to avoid han= ging\n", + spi->max_speed_hz); + return -EINVAL; + } /* * Manually set the Chip Select for the second amp in th= e node. * This is only supported for systems with 2 amps, since we cannot expan= d the @@ -219,8 +232,6 @@ static int generic_dsd_config(struct cs35l41_hda *cs35l= 41, struct device *physde * first. */ if (cfg->cs_gpio_index >=3D 0) { - spi =3D to_spi_device(cs35l41->dev); - if (cfg->num_amps !=3D 2) { dev_warn(cs35l41->dev, "Cannot update SPI CS, Number of Amps (%d) !=3D 2\n", --=20 2.40.1