From nobody Sat Dec 27 11:02:29 2025 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [159.69.200.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A75C20B02; Wed, 20 Dec 2023 10:38:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kernkonzept.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kernkonzept.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernkonzept.com header.i=@kernkonzept.com header.b="PNv9U6YK" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=3RDmDVlnk2mcGyH1E2TgKjgnExaduXtEXQzTUb/7LfE=; b=PNv9U6YK4dcik1VaX+PEEqvsXr RHRqWbas9TGMFLf3Owq7P+rXwsp2q3PJqDY50o9HaG95EpX+AamE90oyZHB4Qi3tzia+8yfmAWAI7 9f3rzI9G5svTx/AiIS5Sf4C020jEaeXvXbb8APIi1l6Xji0mrlOP2jbebBHRW/6lO9WZ3rbDTNvoI WPpnhOZ+lLSXtOsBvUmqqyJYdlLAkOhcxK7xD7fkS5nBToVhQa2euOdgw9gmT/qMbmxrCs4xLuHj2 IQd8UjKTq6itXrAH8kNDmPFPmBK1EEirVOJydrPc5AmPPS0LArncyqzu2WN0e1OsYw7nmYxHGgdmt xPS2jDvA==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1rFtya-00DKtz-0D; Wed, 20 Dec 2023 11:38:56 +0100 From: Stephan Gerhold Date: Wed, 20 Dec 2023 11:38:49 +0100 Subject: [PATCH v2 1/2] dt-bindings: interconnect: Add Qualcomm MSM8909 DT bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231220-icc-msm8909-v2-1-3b68bbed2891@kernkonzept.com> References: <20231220-icc-msm8909-v2-0-3b68bbed2891@kernkonzept.com> In-Reply-To: <20231220-icc-msm8909-v2-0-3b68bbed2891@kernkonzept.com> To: Georgi Djakov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Adam Skladowski , Stephan Gerhold , Krzysztof Kozlowski X-Mailer: b4 0.12.4 From: Adam Skladowski Add bindings for Qualcomm MSM8909 Network-On-Chip interconnect devices. [Stephan: Drop separate mm-snoc that exists downstream since it's actually the same NoC as SNoC in hardware] Signed-off-by: Adam Skladowski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold --- .../devicetree/bindings/interconnect/qcom,rpm.yaml | 3 + include/dt-bindings/interconnect/qcom,msm8909.h | 93 ++++++++++++++++++= ++++ 2 files changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b= /Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 08c1c6b9d7cf..5aaa92a7cef7 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -23,6 +23,9 @@ properties: =20 compatible: enum: + - qcom,msm8909-bimc + - qcom,msm8909-pcnoc + - qcom,msm8909-snoc - qcom,msm8916-bimc - qcom,msm8916-pcnoc - qcom,msm8916-snoc diff --git a/include/dt-bindings/interconnect/qcom,msm8909.h b/include/dt-b= indings/interconnect/qcom,msm8909.h new file mode 100644 index 000000000000..76365d8aec21 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8909.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm MSM8909 interconnect IDs + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H + +/* BIMC fabric */ +#define MAS_APPS_PROC 0 +#define MAS_OXILI 1 +#define MAS_SNOC_BIMC_0 2 +#define MAS_SNOC_BIMC_1 3 +#define MAS_TCU_0 4 +#define MAS_TCU_1 5 +#define SLV_EBI 6 +#define SLV_BIMC_SNOC 7 + +/* PCNOC fabric */ +#define MAS_AUDIO 0 +#define MAS_SPDM 1 +#define MAS_DEHR 2 +#define MAS_QPIC 3 +#define MAS_BLSP_1 4 +#define MAS_USB_HS 5 +#define MAS_CRYPTO 6 +#define MAS_SDCC_1 7 +#define MAS_SDCC_2 8 +#define MAS_SNOC_PCNOC 9 +#define PCNOC_M_0 10 +#define PCNOC_M_1 11 +#define PCNOC_INT_0 12 +#define PCNOC_INT_1 13 +#define PCNOC_S_0 14 +#define PCNOC_S_1 15 +#define PCNOC_S_2 16 +#define PCNOC_S_3 17 +#define PCNOC_S_4 18 +#define PCNOC_S_5 19 +#define PCNOC_S_7 20 +#define SLV_TCSR 21 +#define SLV_SDCC_1 22 +#define SLV_BLSP_1 23 +#define SLV_CRYPTO_0_CFG 24 +#define SLV_MESSAGE_RAM 25 +#define SLV_PDM 26 +#define SLV_PRNG 27 +#define SLV_USB_HS 28 +#define SLV_QPIC 29 +#define SLV_SPDM 30 +#define SLV_SDCC_2 31 +#define SLV_AUDIO 32 +#define SLV_DEHR_CFG 33 +#define SLV_SNOC_CFG 34 +#define SLV_QDSS_CFG 35 +#define SLV_USB_PHY 36 +#define SLV_CAMERA_SS_CFG 37 +#define SLV_DISP_SS_CFG 38 +#define SLV_VENUS_CFG 39 +#define SLV_TLMM 40 +#define SLV_GPU_CFG 41 +#define SLV_IMEM_CFG 42 +#define SLV_BIMC_CFG 43 +#define SLV_PMIC_ARB 44 +#define SLV_TCU 45 +#define SLV_PCNOC_SNOC 46 + +/* SNOC fabric */ +#define MAS_QDSS_BAM 0 +#define MAS_BIMC_SNOC 1 +#define MAS_MDP 2 +#define MAS_PCNOC_SNOC 3 +#define MAS_VENUS 4 +#define MAS_VFE 5 +#define MAS_QDSS_ETR 6 +#define MM_INT_0 7 +#define MM_INT_1 8 +#define MM_INT_2 9 +#define MM_INT_BIMC 10 +#define QDSS_INT 11 +#define SNOC_INT_0 12 +#define SNOC_INT_1 13 +#define SNOC_INT_BIMC 14 +#define SLV_KPSS_AHB 15 +#define SLV_SNOC_BIMC_0 16 +#define SLV_SNOC_BIMC_1 17 +#define SLV_IMEM 18 +#define SLV_SNOC_PCNOC 19 +#define SLV_QDSS_STM 20 +#define SLV_CATS_0 21 +#define SLV_CATS_1 22 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H */ --=20 2.39.2 From nobody Sat Dec 27 11:02:29 2025 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [159.69.200.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 206F620B05; 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Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1rFtyb-00DKtz-1Y; Wed, 20 Dec 2023 11:38:57 +0100 From: Stephan Gerhold Date: Wed, 20 Dec 2023 11:38:50 +0100 Subject: [PATCH v2 2/2] interconnect: qcom: Add MSM8909 interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231220-icc-msm8909-v2-2-3b68bbed2891@kernkonzept.com> References: <20231220-icc-msm8909-v2-0-3b68bbed2891@kernkonzept.com> In-Reply-To: <20231220-icc-msm8909-v2-0-3b68bbed2891@kernkonzept.com> To: Georgi Djakov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Adam Skladowski , Stephan Gerhold X-Mailer: b4 0.12.4 From: Adam Skladowski Add driver for interconnect busses found in MSM8909 based platforms. The topology consists of three NoCs that are partially controlled by a RPM processor. In the downstream/vendor kernel from Qualcomm there is an additional "mm-snoc". However, it actually ends up using the same RPM "snoc_clk" as the normal "snoc". It looks like this is actually the same NoC in hardware and the "mm-snoc" was only defined to assign a different "qcom,util-fact" to increase bandwidth requests by a static margin. In mainline we can represent this by assigning the equivalent "ab_coeff" to all the nodes that are part of "mm-snoc" downstream. Signed-off-by: Adam Skladowski [Stephan: Drop separate mm-snoc that exists downstream since it's actually the same NoC as SNoC in hardware, add qos_offset for BIMC, add ab_coeff for mm-snoc nodes and BIMC] Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8909.c | 1329 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 1340 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 697f96c49f6f..48b1d5434cd0 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -8,6 +8,15 @@ config INTERCONNECT_QCOM config INTERCONNECT_QCOM_BCM_VOTER tristate =20 +config INTERCONNECT_QCOM_MSM8909 + tristate "Qualcomm MSM8909 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8909-based + platforms. + config INTERCONNECT_QCOM_MSM8916 tristate "Qualcomm MSM8916 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 704846165022..83a3c1fc8155 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) +=3D interconnect_qcom.o =20 interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o +qnoc-msm8909-objs :=3D msm8909.o qnoc-msm8916-objs :=3D msm8916.o qnoc-msm8939-objs :=3D msm8939.o qnoc-msm8974-objs :=3D msm8974.o @@ -36,6 +37,7 @@ qnoc-x1e80100-objs :=3D x1e80100.o icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clocks.o =20 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) +=3D qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974.o diff --git a/drivers/interconnect/qcom/msm8909.c b/drivers/interconnect/qco= m/msm8909.c new file mode 100644 index 000000000000..23b1a818d774 --- /dev/null +++ b/drivers/interconnect/qcom/msm8909.c @@ -0,0 +1,1329 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on data from msm8909-bus.dtsi in Qualcomm's msm-3.18 release: + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "icc-rpm.h" + +enum { + QNOC_MASTER_AMPSS_M0 =3D 1, + QNOC_MASTER_GRAPHICS_3D, + QNOC_SNOC_BIMC_0_MAS, + QNOC_SNOC_BIMC_1_MAS, + QNOC_MASTER_TCU_0, + QNOC_MASTER_TCU_1, + QNOC_MASTER_AUDIO, + QNOC_MASTER_SPDM, + QNOC_MASTER_DEHR, + QNOC_MASTER_QPIC, + QNOC_MASTER_BLSP_1, + QNOC_MASTER_USB_HS, + QNOC_MASTER_CRYPTO_CORE0, + QNOC_MASTER_SDCC_1, + QNOC_MASTER_SDCC_2, + QNOC_SNOC_PNOC_MAS, + QNOC_MASTER_QDSS_BAM, + QNOC_BIMC_SNOC_MAS, + QNOC_MASTER_MDP_PORT0, + QNOC_PNOC_SNOC_MAS, + QNOC_MASTER_VIDEO_P0, + QNOC_MASTER_VFE, + QNOC_MASTER_QDSS_ETR, + QNOC_PNOC_M_0, + QNOC_PNOC_M_1, + QNOC_PNOC_INT_0, + QNOC_PNOC_INT_1, + QNOC_PNOC_SLV_0, + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_3, + QNOC_PNOC_SLV_4, + QNOC_PNOC_SLV_5, + QNOC_PNOC_SLV_7, + QNOC_SNOC_MM_INT_0, + QNOC_SNOC_MM_INT_1, + QNOC_SNOC_MM_INT_2, + QNOC_SNOC_MM_INT_BIMC, + QNOC_SNOC_QDSS_INT, + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_INT_BIMC, + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_TCSR, + QNOC_SLAVE_SDCC_1, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_MESSAGE_RAM, + QNOC_SLAVE_PDM, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_QPIC, + QNOC_SLAVE_SPDM, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_AUDIO, + QNOC_SLAVE_DEHR_CFG, + QNOC_SLAVE_SNOC_CFG, + QNOC_SLAVE_QDSS_CFG, + QNOC_SLAVE_USB_PHYS_CFG, + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG, + QNOC_SLAVE_TLMM, + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_IMEM_CFG, + QNOC_SLAVE_BIMC_CFG, + QNOC_SLAVE_PMIC_ARB, + QNOC_SLAVE_TCU, + QNOC_PNOC_SNOC_SLV, + QNOC_SLAVE_APPSS, + QNOC_SNOC_BIMC_0_SLV, + QNOC_SNOC_BIMC_1_SLV, + QNOC_SLAVE_SYSTEM_IMEM, + QNOC_SNOC_PNOC_SLV, + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64, +}; + +static const u16 mas_apps_proc_links[] =3D { + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_apps_proc =3D { + .name =3D "mas_apps_proc", + .id =3D QNOC_MASTER_AMPSS_M0, + .buswidth =3D 8, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_apps_proc_links), + .links =3D mas_apps_proc_links, +}; + +static const u16 mas_oxili_links[] =3D { + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_oxili =3D { + .name =3D "mas_oxili", + .id =3D QNOC_MASTER_GRAPHICS_3D, + .buswidth =3D 8, + .mas_rpm_id =3D 6, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 2, + .num_links =3D ARRAY_SIZE(mas_oxili_links), + .links =3D mas_oxili_links, +}; + +static const u16 mas_snoc_bimc_0_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc_0 =3D { + .name =3D "mas_snoc_bimc_0", + .id =3D QNOC_SNOC_BIMC_0_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 3, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 3, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_0_links), + .links =3D mas_snoc_bimc_0_links, +}; + +static const u16 mas_snoc_bimc_1_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc_1 =3D { + .name =3D "mas_snoc_bimc_1", + .id =3D QNOC_SNOC_BIMC_1_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 76, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 4, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_1_links), + .links =3D mas_snoc_bimc_1_links, +}; + +static const u16 mas_tcu_0_links[] =3D { + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_tcu_0 =3D { + .name =3D "mas_tcu_0", + .id =3D QNOC_MASTER_TCU_0, + .buswidth =3D 8, + .mas_rpm_id =3D 102, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 2, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(mas_tcu_0_links), + .links =3D mas_tcu_0_links, +}; + +static const u16 mas_tcu_1_links[] =3D { + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_tcu_1 =3D { + .name =3D "mas_tcu_1", + .id =3D QNOC_MASTER_TCU_1, + .buswidth =3D 8, + .mas_rpm_id =3D 103, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 2, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(mas_tcu_1_links), + .links =3D mas_tcu_1_links, +}; + +static const u16 mas_audio_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_audio =3D { + .name =3D "mas_audio", + .id =3D QNOC_MASTER_AUDIO, + .buswidth =3D 4, + .mas_rpm_id =3D 78, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_audio_links), + .links =3D mas_audio_links, +}; + +static const u16 mas_spdm_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_spdm =3D { + .name =3D "mas_spdm", + .id =3D QNOC_MASTER_SPDM, + .buswidth =3D 4, + .mas_rpm_id =3D 50, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_spdm_links), + .links =3D mas_spdm_links, +}; + +static const u16 mas_dehr_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_dehr =3D { + .name =3D "mas_dehr", + .id =3D QNOC_MASTER_DEHR, + .buswidth =3D 4, + .mas_rpm_id =3D 48, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_dehr_links), + .links =3D mas_dehr_links, +}; + +static const u16 mas_qpic_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_qpic =3D { + .name =3D "mas_qpic", + .id =3D QNOC_MASTER_QPIC, + .buswidth =3D 4, + .mas_rpm_id =3D 58, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_qpic_links), + .links =3D mas_qpic_links, +}; + +static const u16 mas_blsp_1_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_1 =3D { + .name =3D "mas_blsp_1", + .id =3D QNOC_MASTER_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D 41, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_1_links), + .links =3D mas_blsp_1_links, +}; + +static const u16 mas_usb_hs_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_usb_hs =3D { + .name =3D "mas_usb_hs", + .id =3D QNOC_MASTER_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D 42, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hs_links), + .links =3D mas_usb_hs_links, +}; + +static const u16 mas_crypto_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_crypto =3D { + .name =3D "mas_crypto", + .id =3D QNOC_MASTER_CRYPTO_CORE0, + .buswidth =3D 8, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_crypto_links), + .links =3D mas_crypto_links, +}; + +static const u16 mas_sdcc_1_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_1 =3D { + .name =3D "mas_sdcc_1", + .id =3D QNOC_MASTER_SDCC_1, + .buswidth =3D 8, + .mas_rpm_id =3D 33, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_sdcc_1_links), + .links =3D mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_2 =3D { + .name =3D "mas_sdcc_2", + .id =3D QNOC_MASTER_SDCC_2, + .buswidth =3D 8, + .mas_rpm_id =3D 35, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_sdcc_2_links), + .links =3D mas_sdcc_2_links, +}; + +static const u16 mas_snoc_pcnoc_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_snoc_pcnoc =3D { + .name =3D "mas_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 77, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_snoc_pcnoc_links), + .links =3D mas_snoc_pcnoc_links, +}; + +static const u16 mas_qdss_bam_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam =3D { + .name =3D "mas_qdss_bam", + .id =3D QNOC_MASTER_QDSS_BAM, + .buswidth =3D 4, + .mas_rpm_id =3D 19, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 11, + .num_links =3D ARRAY_SIZE(mas_qdss_bam_links), + .links =3D mas_qdss_bam_links, +}; + +static const u16 mas_bimc_snoc_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1 +}; + +static struct qcom_icc_node mas_bimc_snoc =3D { + .name =3D "mas_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 21, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_bimc_snoc_links), + .links =3D mas_bimc_snoc_links, +}; + +static const u16 mas_mdp_links[] =3D { + QNOC_SNOC_MM_INT_1, + QNOC_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_mdp =3D { + .name =3D "mas_mdp", + .id =3D QNOC_MASTER_MDP_PORT0, + .buswidth =3D 16, + .mas_rpm_id =3D 8, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_mdp_links), + .links =3D mas_mdp_links, + .ab_coeff =3D 167, +}; + +static const u16 mas_pcnoc_snoc_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_INT_BIMC +}; + +static struct qcom_icc_node mas_pcnoc_snoc =3D { + .name =3D "mas_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 29, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(mas_pcnoc_snoc_links), + .links =3D mas_pcnoc_snoc_links, +}; + +static const u16 mas_venus_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_venus =3D { + .name =3D "mas_venus", + .id =3D QNOC_MASTER_VIDEO_P0, + .buswidth =3D 16, + .mas_rpm_id =3D 9, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_venus_links), + .links =3D mas_venus_links, + .ab_coeff =3D 167, +}; + +static const u16 mas_vfe_links[] =3D { + QNOC_SNOC_MM_INT_1, + QNOC_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_vfe =3D { + .name =3D "mas_vfe", + .id =3D QNOC_MASTER_VFE, + .buswidth =3D 16, + .mas_rpm_id =3D 11, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_vfe_links), + .links =3D mas_vfe_links, + .ab_coeff =3D 167, +}; + +static const u16 mas_qdss_etr_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr =3D { + .name =3D "mas_qdss_etr", + .id =3D QNOC_MASTER_QDSS_ETR, + .buswidth =3D 8, + .mas_rpm_id =3D 31, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 10, + .num_links =3D ARRAY_SIZE(mas_qdss_etr_links), + .links =3D mas_qdss_etr_links, +}; + +static const u16 pcnoc_m_0_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_m_0 =3D { + .name =3D "pcnoc_m_0", + .id =3D QNOC_PNOC_M_0, + .buswidth =3D 8, + .mas_rpm_id =3D 87, + .slv_rpm_id =3D 116, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(pcnoc_m_0_links), + .links =3D pcnoc_m_0_links, +}; + +static const u16 pcnoc_m_1_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_m_1 =3D { + .name =3D "pcnoc_m_1", + .id =3D QNOC_PNOC_M_1, + .buswidth =3D 8, + .mas_rpm_id =3D 88, + .slv_rpm_id =3D 117, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(pcnoc_m_1_links), + .links =3D pcnoc_m_1_links, +}; + +static const u16 pcnoc_int_0_links[] =3D { + QNOC_PNOC_SLV_3, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_0, + QNOC_PNOC_SLV_7, + QNOC_PNOC_SLV_5, + QNOC_PNOC_SLV_4, + QNOC_SLAVE_TCU +}; + +static struct qcom_icc_node pcnoc_int_0 =3D { + .name =3D "pcnoc_int_0", + .id =3D QNOC_PNOC_INT_0, + .buswidth =3D 8, + .mas_rpm_id =3D 85, + .slv_rpm_id =3D 114, + .num_links =3D ARRAY_SIZE(pcnoc_int_0_links), + .links =3D pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_1_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_int_1 =3D { + .name =3D "pcnoc_int_1", + .id =3D QNOC_PNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 86, + .slv_rpm_id =3D 115, + .num_links =3D ARRAY_SIZE(pcnoc_int_1_links), + .links =3D pcnoc_int_1_links, +}; + +static const u16 pcnoc_s_0_links[] =3D { + QNOC_SLAVE_SDCC_1, + QNOC_SLAVE_TCSR, + QNOC_SLAVE_BLSP_1 +}; + +static struct qcom_icc_node pcnoc_s_0 =3D { + .name =3D "pcnoc_s_0", + .id =3D QNOC_PNOC_SLV_0, + .buswidth =3D 4, + .mas_rpm_id =3D 89, + .slv_rpm_id =3D 118, + .num_links =3D ARRAY_SIZE(pcnoc_s_0_links), + .links =3D pcnoc_s_0_links, +}; + +static const u16 pcnoc_s_1_links[] =3D { + QNOC_SLAVE_MESSAGE_RAM, + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_PDM, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_QPIC +}; + +static struct qcom_icc_node pcnoc_s_1 =3D { + .name =3D "pcnoc_s_1", + .id =3D QNOC_PNOC_SLV_1, + .buswidth =3D 4, + .mas_rpm_id =3D 90, + .slv_rpm_id =3D 119, + .num_links =3D ARRAY_SIZE(pcnoc_s_1_links), + .links =3D pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] =3D { + QNOC_SLAVE_SPDM, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_AUDIO, + QNOC_SLAVE_DEHR_CFG +}; + +static struct qcom_icc_node pcnoc_s_2 =3D { + .name =3D "pcnoc_s_2", + .id =3D QNOC_PNOC_SLV_2, + .buswidth =3D 4, + .mas_rpm_id =3D 91, + .slv_rpm_id =3D 120, + .num_links =3D ARRAY_SIZE(pcnoc_s_2_links), + .links =3D pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] =3D { + QNOC_SLAVE_QDSS_CFG, + QNOC_SLAVE_USB_PHYS_CFG, + QNOC_SLAVE_SNOC_CFG +}; + +static struct qcom_icc_node pcnoc_s_3 =3D { + .name =3D "pcnoc_s_3", + .id =3D QNOC_PNOC_SLV_3, + .buswidth =3D 4, + .mas_rpm_id =3D 92, + .slv_rpm_id =3D 121, + .num_links =3D ARRAY_SIZE(pcnoc_s_3_links), + .links =3D pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] =3D { + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 =3D { + .name =3D "pcnoc_s_4", + .id =3D QNOC_PNOC_SLV_4, + .buswidth =3D 4, + .mas_rpm_id =3D 93, + .slv_rpm_id =3D 122, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(pcnoc_s_4_links), + .links =3D pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_5_links[] =3D { + QNOC_SLAVE_TLMM +}; + +static struct qcom_icc_node pcnoc_s_5 =3D { + .name =3D "pcnoc_s_5", + .id =3D QNOC_PNOC_SLV_5, + .buswidth =3D 4, + .mas_rpm_id =3D 129, + .slv_rpm_id =3D 189, + .num_links =3D ARRAY_SIZE(pcnoc_s_5_links), + .links =3D pcnoc_s_5_links, +}; + +static const u16 pcnoc_s_7_links[] =3D { + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_IMEM_CFG, + QNOC_SLAVE_BIMC_CFG, + QNOC_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_7 =3D { + .name =3D "pcnoc_s_7", + .id =3D QNOC_PNOC_SLV_7, + .buswidth =3D 4, + .mas_rpm_id =3D 95, + .slv_rpm_id =3D 124, + .num_links =3D ARRAY_SIZE(pcnoc_s_7_links), + .links =3D pcnoc_s_7_links, +}; + +static const u16 mm_int_0_links[] =3D { + QNOC_SNOC_MM_INT_BIMC +}; + +static struct qcom_icc_node mm_int_0 =3D { + .name =3D "mm_int_0", + .id =3D QNOC_SNOC_MM_INT_0, + .buswidth =3D 16, + .mas_rpm_id =3D 79, + .slv_rpm_id =3D 108, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mm_int_0_links), + .links =3D mm_int_0_links, + .ab_coeff =3D 167, +}; + +static const u16 mm_int_1_links[] =3D { + QNOC_SNOC_MM_INT_BIMC +}; + +static struct qcom_icc_node mm_int_1 =3D { + .name =3D "mm_int_1", + .id =3D QNOC_SNOC_MM_INT_1, + .buswidth =3D 16, + .mas_rpm_id =3D 80, + .slv_rpm_id =3D 109, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mm_int_1_links), + .links =3D mm_int_1_links, + .ab_coeff =3D 167, +}; + +static const u16 mm_int_2_links[] =3D { + QNOC_SNOC_INT_0 +}; + +static struct qcom_icc_node mm_int_2 =3D { + .name =3D "mm_int_2", + .id =3D QNOC_SNOC_MM_INT_2, + .buswidth =3D 16, + .mas_rpm_id =3D 81, + .slv_rpm_id =3D 110, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mm_int_2_links), + .links =3D mm_int_2_links, + .ab_coeff =3D 167, +}; + +static const u16 mm_int_bimc_links[] =3D { + QNOC_SNOC_BIMC_1_SLV +}; + +static struct qcom_icc_node mm_int_bimc =3D { + .name =3D "mm_int_bimc", + .id =3D QNOC_SNOC_MM_INT_BIMC, + .buswidth =3D 16, + .mas_rpm_id =3D 82, + .slv_rpm_id =3D 111, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mm_int_bimc_links), + .links =3D mm_int_bimc_links, + .ab_coeff =3D 167, +}; + +static const u16 qdss_int_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_BIMC +}; + +static struct qcom_icc_node qdss_int =3D { + .name =3D "qdss_int", + .id =3D QNOC_SNOC_QDSS_INT, + .buswidth =3D 8, + .mas_rpm_id =3D 98, + .slv_rpm_id =3D 128, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(qdss_int_links), + .links =3D qdss_int_links, +}; + +static const u16 snoc_int_0_links[] =3D { + QNOC_SLAVE_SYSTEM_IMEM, + QNOC_SLAVE_QDSS_STM, + QNOC_SNOC_PNOC_SLV +}; + +static struct qcom_icc_node snoc_int_0 =3D { + .name =3D "snoc_int_0", + .id =3D QNOC_SNOC_INT_0, + .buswidth =3D 8, + .mas_rpm_id =3D 99, + .slv_rpm_id =3D 130, + .num_links =3D ARRAY_SIZE(snoc_int_0_links), + .links =3D snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] =3D { + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_APPSS, + QNOC_SLAVE_OCMEM_64 +}; + +static struct qcom_icc_node snoc_int_1 =3D { + .name =3D "snoc_int_1", + .id =3D QNOC_SNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 100, + .slv_rpm_id =3D 131, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(snoc_int_1_links), + .links =3D snoc_int_1_links, +}; + +static const u16 snoc_int_bimc_links[] =3D { + QNOC_SNOC_BIMC_0_SLV +}; + +static struct qcom_icc_node snoc_int_bimc =3D { + .name =3D "snoc_int_bimc", + .id =3D QNOC_SNOC_INT_BIMC, + .buswidth =3D 8, + .mas_rpm_id =3D 101, + .slv_rpm_id =3D 132, + .num_links =3D ARRAY_SIZE(snoc_int_bimc_links), + .links =3D snoc_int_bimc_links, +}; + +static struct qcom_icc_node slv_ebi =3D { + .name =3D "slv_ebi", + .id =3D QNOC_SLAVE_EBI_CH0, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static const u16 slv_bimc_snoc_links[] =3D { + QNOC_BIMC_SNOC_MAS +}; + +static struct qcom_icc_node slv_bimc_snoc =3D { + .name =3D "slv_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 2, + .num_links =3D ARRAY_SIZE(slv_bimc_snoc_links), + .links =3D slv_bimc_snoc_links, +}; + +static struct qcom_icc_node slv_tcsr =3D { + .name =3D "slv_tcsr", + .id =3D QNOC_SLAVE_TCSR, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 50, +}; + +static struct qcom_icc_node slv_sdcc_1 =3D { + .name =3D "slv_sdcc_1", + .id =3D QNOC_SLAVE_SDCC_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 31, +}; + +static struct qcom_icc_node slv_blsp_1 =3D { + .name =3D "slv_blsp_1", + .id =3D QNOC_SLAVE_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 39, +}; + +static struct qcom_icc_node slv_crypto_0_cfg =3D { + .name =3D "slv_crypto_0_cfg", + .id =3D QNOC_SLAVE_CRYPTO_0_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 52, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_message_ram =3D { + .name =3D "slv_message_ram", + .id =3D QNOC_SLAVE_MESSAGE_RAM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 55, +}; + +static struct qcom_icc_node slv_pdm =3D { + .name =3D "slv_pdm", + .id =3D QNOC_SLAVE_PDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 41, +}; + +static struct qcom_icc_node slv_prng =3D { + .name =3D "slv_prng", + .id =3D QNOC_SLAVE_PRNG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 44, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_usb_hs =3D { + .name =3D "slv_usb_hs", + .id =3D QNOC_SLAVE_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 40, +}; + +static struct qcom_icc_node slv_qpic =3D { + .name =3D "slv_qpic", + .id =3D QNOC_SLAVE_QPIC, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 80, +}; + +static struct qcom_icc_node slv_spdm =3D { + .name =3D "slv_spdm", + .id =3D QNOC_SLAVE_SPDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 60, +}; + +static struct qcom_icc_node slv_sdcc_2 =3D { + .name =3D "slv_sdcc_2", + .id =3D QNOC_SLAVE_SDCC_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 33, +}; + +static struct qcom_icc_node slv_audio =3D { + .name =3D "slv_audio", + .id =3D QNOC_SLAVE_AUDIO, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 105, +}; + +static struct qcom_icc_node slv_dehr_cfg =3D { + .name =3D "slv_dehr_cfg", + .id =3D QNOC_SLAVE_DEHR_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 61, +}; + +static struct qcom_icc_node slv_snoc_cfg =3D { + .name =3D "slv_snoc_cfg", + .id =3D QNOC_SLAVE_SNOC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 70, +}; + +static struct qcom_icc_node slv_qdss_cfg =3D { + .name =3D "slv_qdss_cfg", + .id =3D QNOC_SLAVE_QDSS_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 63, +}; + +static struct qcom_icc_node slv_usb_phy =3D { + .name =3D "slv_usb_phy", + .id =3D QNOC_SLAVE_USB_PHYS_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 95, +}; + +static struct qcom_icc_node slv_camera_ss_cfg =3D { + .name =3D "slv_camera_ss_cfg", + .id =3D QNOC_SLAVE_CAMERA_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 3, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_disp_ss_cfg =3D { + .name =3D "slv_disp_ss_cfg", + .id =3D QNOC_SLAVE_DISPLAY_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 4, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_venus_cfg =3D { + .name =3D "slv_venus_cfg", + .id =3D QNOC_SLAVE_VENUS_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 10, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_tlmm =3D { + .name =3D "slv_tlmm", + .id =3D QNOC_SLAVE_TLMM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 51, +}; + +static struct qcom_icc_node slv_gpu_cfg =3D { + .name =3D "slv_gpu_cfg", + .id =3D QNOC_SLAVE_GRAPHICS_3D_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 11, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_imem_cfg =3D { + .name =3D "slv_imem_cfg", + .id =3D QNOC_SLAVE_IMEM_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 54, +}; + +static struct qcom_icc_node slv_bimc_cfg =3D { + .name =3D "slv_bimc_cfg", + .id =3D QNOC_SLAVE_BIMC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 56, +}; + +static struct qcom_icc_node slv_pmic_arb =3D { + .name =3D "slv_pmic_arb", + .id =3D QNOC_SLAVE_PMIC_ARB, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 59, +}; + +static struct qcom_icc_node slv_tcu =3D { + .name =3D "slv_tcu", + .id =3D QNOC_SLAVE_TCU, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 133, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static const u16 slv_pcnoc_snoc_links[] =3D { + QNOC_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node slv_pcnoc_snoc =3D { + .name =3D "slv_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 45, + .num_links =3D ARRAY_SIZE(slv_pcnoc_snoc_links), + .links =3D slv_pcnoc_snoc_links, +}; + +static struct qcom_icc_node slv_kpss_ahb =3D { + .name =3D "slv_kpss_ahb", + .id =3D QNOC_SLAVE_APPSS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 20, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static const u16 slv_snoc_bimc_0_links[] =3D { + QNOC_SNOC_BIMC_0_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc_0 =3D { + .name =3D "slv_snoc_bimc_0", + .id =3D QNOC_SNOC_BIMC_0_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 24, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_0_links), + .links =3D slv_snoc_bimc_0_links, +}; + +static const u16 slv_snoc_bimc_1_links[] =3D { + QNOC_SNOC_BIMC_1_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc_1 =3D { + .name =3D "slv_snoc_bimc_1", + .id =3D QNOC_SNOC_BIMC_1_SLV, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 104, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_1_links), + .links =3D slv_snoc_bimc_1_links, +}; + +static struct qcom_icc_node slv_imem =3D { + .name =3D "slv_imem", + .id =3D QNOC_SLAVE_SYSTEM_IMEM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static const u16 slv_snoc_pcnoc_links[] =3D { + QNOC_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node slv_snoc_pcnoc =3D { + .name =3D "slv_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 28, + .num_links =3D ARRAY_SIZE(slv_snoc_pcnoc_links), + .links =3D slv_snoc_pcnoc_links, +}; + +static struct qcom_icc_node slv_qdss_stm =3D { + .name =3D "slv_qdss_stm", + .id =3D QNOC_SLAVE_QDSS_STM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; + +static struct qcom_icc_node slv_cats_0 =3D { + .name =3D "slv_cats_0", + .id =3D QNOC_SLAVE_CATS_128, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 106, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_cats_1 =3D { + .name =3D "slv_cats_1", + .id =3D QNOC_SLAVE_OCMEM_64, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 107, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node *msm8909_bimc_nodes[] =3D { + [MAS_APPS_PROC] =3D &mas_apps_proc, + [MAS_OXILI] =3D &mas_oxili, + [MAS_SNOC_BIMC_0] =3D &mas_snoc_bimc_0, + [MAS_SNOC_BIMC_1] =3D &mas_snoc_bimc_1, + [MAS_TCU_0] =3D &mas_tcu_0, + [MAS_TCU_1] =3D &mas_tcu_1, + [SLV_EBI] =3D &slv_ebi, + [SLV_BIMC_SNOC] =3D &slv_bimc_snoc, +}; + +static const struct regmap_config msm8909_bimc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x62000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8909_bimc =3D { + .type =3D QCOM_ICC_BIMC, + .nodes =3D msm8909_bimc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8909_bimc_nodes), + .bus_clk_desc =3D &bimc_clk, + .regmap_cfg =3D &msm8909_bimc_regmap_config, + .qos_offset =3D 0x8000, + .ab_coeff =3D 154, +}; + +static struct qcom_icc_node *msm8909_pcnoc_nodes[] =3D { + [MAS_AUDIO] =3D &mas_audio, + [MAS_SPDM] =3D &mas_spdm, + [MAS_DEHR] =3D &mas_dehr, + [MAS_QPIC] =3D &mas_qpic, + [MAS_BLSP_1] =3D &mas_blsp_1, + [MAS_USB_HS] =3D &mas_usb_hs, + [MAS_CRYPTO] =3D &mas_crypto, + [MAS_SDCC_1] =3D &mas_sdcc_1, + [MAS_SDCC_2] =3D &mas_sdcc_2, + [MAS_SNOC_PCNOC] =3D &mas_snoc_pcnoc, + [PCNOC_M_0] =3D &pcnoc_m_0, + [PCNOC_M_1] =3D &pcnoc_m_1, + [PCNOC_INT_0] =3D &pcnoc_int_0, + [PCNOC_INT_1] =3D &pcnoc_int_1, + [PCNOC_S_0] =3D &pcnoc_s_0, + [PCNOC_S_1] =3D &pcnoc_s_1, + [PCNOC_S_2] =3D &pcnoc_s_2, + [PCNOC_S_3] =3D &pcnoc_s_3, + [PCNOC_S_4] =3D &pcnoc_s_4, + [PCNOC_S_5] =3D &pcnoc_s_5, + [PCNOC_S_7] =3D &pcnoc_s_7, + [SLV_TCSR] =3D &slv_tcsr, + [SLV_SDCC_1] =3D &slv_sdcc_1, + [SLV_BLSP_1] =3D &slv_blsp_1, + [SLV_CRYPTO_0_CFG] =3D &slv_crypto_0_cfg, + [SLV_MESSAGE_RAM] =3D &slv_message_ram, + [SLV_PDM] =3D &slv_pdm, + [SLV_PRNG] =3D &slv_prng, + [SLV_USB_HS] =3D &slv_usb_hs, + [SLV_QPIC] =3D &slv_qpic, + [SLV_SPDM] =3D &slv_spdm, + [SLV_SDCC_2] =3D &slv_sdcc_2, + [SLV_AUDIO] =3D &slv_audio, + [SLV_DEHR_CFG] =3D &slv_dehr_cfg, + [SLV_SNOC_CFG] =3D &slv_snoc_cfg, + [SLV_QDSS_CFG] =3D &slv_qdss_cfg, + [SLV_USB_PHY] =3D &slv_usb_phy, + [SLV_CAMERA_SS_CFG] =3D &slv_camera_ss_cfg, + [SLV_DISP_SS_CFG] =3D &slv_disp_ss_cfg, + [SLV_VENUS_CFG] =3D &slv_venus_cfg, + [SLV_TLMM] =3D &slv_tlmm, + [SLV_GPU_CFG] =3D &slv_gpu_cfg, + [SLV_IMEM_CFG] =3D &slv_imem_cfg, + [SLV_BIMC_CFG] =3D &slv_bimc_cfg, + [SLV_PMIC_ARB] =3D &slv_pmic_arb, + [SLV_TCU] =3D &slv_tcu, + [SLV_PCNOC_SNOC] =3D &slv_pcnoc_snoc, +}; + +static const struct regmap_config msm8909_pcnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x11000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8909_pcnoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8909_pcnoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8909_pcnoc_nodes), + .bus_clk_desc =3D &bus_0_clk, + .regmap_cfg =3D &msm8909_pcnoc_regmap_config, + .qos_offset =3D 0x7000, +}; + +static struct qcom_icc_node *msm8909_snoc_nodes[] =3D { + [MAS_QDSS_BAM] =3D &mas_qdss_bam, + [MAS_BIMC_SNOC] =3D &mas_bimc_snoc, + [MAS_MDP] =3D &mas_mdp, + [MAS_PCNOC_SNOC] =3D &mas_pcnoc_snoc, + [MAS_VENUS] =3D &mas_venus, + [MAS_VFE] =3D &mas_vfe, + [MAS_QDSS_ETR] =3D &mas_qdss_etr, + [MM_INT_0] =3D &mm_int_0, + [MM_INT_1] =3D &mm_int_1, + [MM_INT_2] =3D &mm_int_2, + [MM_INT_BIMC] =3D &mm_int_bimc, + [QDSS_INT] =3D &qdss_int, + [SNOC_INT_0] =3D &snoc_int_0, + [SNOC_INT_1] =3D &snoc_int_1, + [SNOC_INT_BIMC] =3D &snoc_int_bimc, + [SLV_KPSS_AHB] =3D &slv_kpss_ahb, + [SLV_SNOC_BIMC_0] =3D &slv_snoc_bimc_0, + [SLV_SNOC_BIMC_1] =3D &slv_snoc_bimc_1, + [SLV_IMEM] =3D &slv_imem, + [SLV_SNOC_PCNOC] =3D &slv_snoc_pcnoc, + [SLV_QDSS_STM] =3D &slv_qdss_stm, + [SLV_CATS_0] =3D &slv_cats_0, + [SLV_CATS_1] =3D &slv_cats_1, +}; + +static const struct regmap_config msm8909_snoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x13000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8909_snoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8909_snoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8909_snoc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .regmap_cfg =3D &msm8909_snoc_regmap_config, + .qos_offset =3D 0x7000, +}; + +static const struct of_device_id msm8909_noc_of_match[] =3D { + { .compatible =3D "qcom,msm8909-bimc", .data =3D &msm8909_bimc }, + { .compatible =3D "qcom,msm8909-pcnoc", .data =3D &msm8909_pcnoc }, + { .compatible =3D "qcom,msm8909-snoc", .data =3D &msm8909_snoc }, + { } +}; +MODULE_DEVICE_TABLE(of, msm8909_noc_of_match); + +static struct platform_driver msm8909_noc_driver =3D { + .probe =3D qnoc_probe, + .remove_new =3D qnoc_remove, + .driver =3D { + .name =3D "qnoc-msm8909", + .of_match_table =3D msm8909_noc_of_match, + .sync_state =3D icc_sync_state, + }, +}; +module_platform_driver(msm8909_noc_driver); + +MODULE_DESCRIPTION("Qualcomm MSM8909 NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.39.2