From nobody Fri Dec 19 12:31:34 2025 Received: from mx0b-00069f02.pphosted.com (mx0b-00069f02.pphosted.com [205.220.177.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E696220DC4 for ; Tue, 19 Dec 2023 15:12:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oracle.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oracle.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b="OlczGLQw" Received: from pps.filterd (m0246631.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BJ9wuhv017135; Tue, 19 Dec 2023 15:12:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=corp-2023-11-20; bh=7NuuEtCagypjfe1xtc4mlaQysed4lhnQXPrzUeLCbiE=; b=OlczGLQwnNuot5L8T2BLKhFGkcOuWfvmwsZrjpY0iNulSNEp25TfcgnS/kvTVkOrmHEr lv+/pMfXjnEIW4ooY8eEgGZIoR4UHmKZuwiqtjKrgqTWx9GtucX+QUSXwWp183gH6k4C 2onrW5wCjMOspWus4QaCcz8g7+gIIXMpOEJ1TAydyXz3TX/vwDZLnFBYR+FsVUeyEAQL haX84pt94Pf511Iq3v+qZgFeCmSa9hxoJbBHwtl549UkXQ/Mz3toRPukRRNNmXW8B6to OeIhbAKab527mSXIdbr4NK+vp6HjYR6rZpIoD5CMCMDLd933kaaloewBzQy4gpe1Rt/B rg== Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.appoci.oracle.com [138.1.37.129]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3v12p465px-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 19 Dec 2023 15:12:27 +0000 Received: from pps.filterd (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 3BJDuAKW028981; Tue, 19 Dec 2023 15:12:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 3v12b6w7p2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 19 Dec 2023 15:12:26 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3BJF7SdV008899; Tue, 19 Dec 2023 15:12:26 GMT Received: from localhost.localdomain (dhcp-10-175-58-169.vpn.oracle.com [10.175.58.169]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 3v12b6w71u-6; Tue, 19 Dec 2023 15:12:25 +0000 From: Vegard Nossum To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-kernel@vger.kernel.org, Brian Gerst , Peter Zijlstra , Linus Torvalds , Vegard Nossum Subject: [PATCH 5/5] x86: add DB flag to 32-bit percpu GDT entry Date: Tue, 19 Dec 2023 16:12:00 +0100 Message-Id: <20231219151200.2878271-6-vegard.nossum@oracle.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219151200.2878271-1-vegard.nossum@oracle.com> References: <20231219151200.2878271-1-vegard.nossum@oracle.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-19_08,2023-12-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 adultscore=0 malwarescore=0 phishscore=0 mlxscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2312190113 X-Proofpoint-GUID: 5IeiefAD5OtgnnxlBoEVhp68y83iybXq X-Proofpoint-ORIG-GUID: 5IeiefAD5OtgnnxlBoEVhp68y83iybXq Content-Type: text/plain; charset="utf-8" The D/B size flag for the 32-bit percpu GDT entry was not set. The Intel manual (vol 3, section 3.4.5) only specifies the meaning of this flag for three cases: 1) code segments used for %cs -- doesn't apply here 2) stack segments used for %ss -- doesn't apply 3) expand-down data segments -- but we don't have the expand-down flag set, so it also doesn't apply here The flag likely doesn't do anything here, although the manual does also say: "This flag should always be set to 1 for 32-bit code and data segments [...]" so we should probably do it anyway. Link: https://lore.kernel.org/all/CAHk-=3Dwib5XLebuEra7y2YH96wxdk=3D8vJnA8X= oVq0FExpzVvN=3DQ@mail.gmail.com/ Signed-off-by: Vegard Nossum --- arch/x86/kernel/setup_percpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c index f2583de97a64..b30d6e180df7 100644 --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -106,7 +106,7 @@ void __init pcpu_populate_pte(unsigned long addr) static inline void setup_percpu_segment(int cpu) { #ifdef CONFIG_X86_32 - struct desc_struct d =3D GDT_ENTRY_INIT(DESC_DATA32 & ~_DESC_DB, + struct desc_struct d =3D GDT_ENTRY_INIT(DESC_DATA32, per_cpu_offset(cpu), 0xFFFFF); =20 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_PERCPU, &d, DESCTYPE_S); --=20 2.34.1