From nobody Sat Dec 27 11:02:25 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A58FF39AF2 for ; Tue, 19 Dec 2023 20:55:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uddosf+j" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40c48d7a7a7so47074595e9.3 for ; Tue, 19 Dec 2023 12:55:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703019336; x=1703624136; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DzAkdCe8GmigS9meJGB6RLFDC8CgmK6hEzQqiVyayPM=; b=uddosf+jbXLcKzhbX/ivgEUQN4ZlabMSEJt5XmFJBg9dtHyZdcDItKCI+snQaab+Nt b1cqa10J5dsC6QpfjteuCLT7ozH10aP6b5UTKlHdFdmZ3Fs6vFbD7V1HUFxf5hpdzeCk jja5nJJL3Qnp48nl0B1HluKA7KkbVde+8axMNxbzTVLOBw5+N6BKuymGI0EeVmWD9Gui d92F3VOkIkGMtYygfZsc+JYS4y7TBAhpZyec9MwBZTOv0atnuK9i6A7mwySXttQpTMGo 9ptxof6O6m/tIEqdxF2oDQQzziJA64F+VHAqqEo7R5lwP2ec24EoyOHyk3ZSEzM4CSug I/xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703019336; x=1703624136; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DzAkdCe8GmigS9meJGB6RLFDC8CgmK6hEzQqiVyayPM=; b=EI4aaE8D/h76OX999XRn+wPB7kR6K2zsYb2/Q7PppSIRyZjOgaj2sBHKPuyyNS9ESw YkvpZrqujGPp3VTJ6jLCFI8DQxITRaIVDvLZ01bX2D2BKM1Af4FgL88r4t/WNKi3VVIk 8r8mMHRQg6DBNMlat7bz46a4h7ReONOj1zd1RjBg5a2Ei7YMddjEd/VCKyMJ3Er6gjUE gKd93Wlngo2xB3r9k4YkR1QJEQgi3T6PSQdRM+Ij2xVdwFxVUSac9yurbTu4m8gfYlD3 K9/44ctbZp4bThiGAbnndh+c+Q8R77VZ94MR5GBBQ+YTQHvkJepuwOTMNwYDAhfl0+F1 1PRg== X-Gm-Message-State: AOJu0YzmZDLt/7AGDZL3t/BFvjFTSDfLPl2DU3IYELsem8sezszzGM8O lax2PyFPRob9Gvp4HRzUH8eK4g== X-Google-Smtp-Source: AGHT+IGAJyStX1mtUQYYCTDSpkc//MycAPf4K9KBlbCHttgWpVCxlYFIAZezQfFFL8nPZ/38jCJ+tg== X-Received: by 2002:a05:600c:4fc5:b0:40c:3f1e:169d with SMTP id o5-20020a05600c4fc500b0040c3f1e169dmr10096872wmq.66.1703019335958; Tue, 19 Dec 2023 12:55:35 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id v16-20020a05600c471000b0040c4886f254sm4460701wmo.13.2023.12.19.12.55.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 12:55:35 -0800 (PST) From: Abel Vesa Date: Tue, 19 Dec 2023 22:55:22 +0200 Subject: [PATCH 1/3] dt-bindings: phy: Add PHY_TYPE_EDP definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231219-x1e80100-phy-edp-compatible-refactor-v1-1-f9e77752953d@linaro.org> References: <20231219-x1e80100-phy-edp-compatible-refactor-v1-0-f9e77752953d@linaro.org> In-Reply-To: <20231219-x1e80100-phy-edp-compatible-refactor-v1-0-f9e77752953d@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Johan Hovold Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=559; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Hwpu6tM6RD/JKvU7jn8nmPGWlA4+6aqHXvdwplMfgcU=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlggNBNofmUvB1GlykPY4ZZ9ztP/pkhjzjIy3Nl Z7srTQrFC6JAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZYIDQQAKCRAbX0TJAJUV VrC0D/9/zHvjOnobv+UQaalKS5+3SEoZw+gq6TlvFolwexpYugxNO9wiiksvlFfKDkrAY+pYWwr QID6451I3+aswqA45oML4NK4NCm49L45Fa9L/u3mYrW71hc0WhTSmF3W9hd+Z9SN6yP36AS+SKn cW082AZxr+L5l3LD4RMz6nFc5u4/Ch/Dj5ez67yoKtbeFWiFIkVKgGnwBz3rnZoYayXz1sHYf5R Ac2NRYU8NSGQWebJcwwLf3kGDxhucoUkjpn5IiwrpXPl1d384F/eB05QMHoLP/jVChE15eGrbvB jd0AxSTImUiVh93vI5268j3Sql9GP3CNEIDtIu3BQtQM63u9qJK4OB5FrEAz9VOpqY+pdhAmP9X wdcDE3kzYo/HYhQA3At+OlvOzF8uhO0hkG4oG2p77PlA4fJ5kIrfb32ag6yUXDHng8PLf0uzFwY nRT33fmT29Q4l1Vlzzmv8BdK36igDs8DPAKuLJH1CO/PsJe9L7o/6x3wf+0URcfNoXiJOKH/Ef6 vtSXzeXZsJQ3fcibxVVbOjit9SUjV6FFe4JkRDDj8xZtrMCMuJl6RchB+FSw75d+JoQNwnhw+U8 EdtrfK5ksdjg8Y676fDntQOdIOGzxwOXiaTLn2E0cRhD2DUF97IcFeuwXkEexKYViS3srXKydSe uzGKeMdgVH1wPxg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add definition for Embedded DisplayPort (eDP) phy type. Signed-off-by: Abel Vesa Acked-by: Krzysztof Kozlowski --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 6b901b342348..b1a64508d937 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -23,5 +23,6 @@ #define PHY_TYPE_DPHY 10 #define PHY_TYPE_CPHY 11 #define PHY_TYPE_USXGMII 12 +#define PHY_TYPE_EDP 13 =20 #endif /* _DT_BINDINGS_PHY */ --=20 2.34.1 From nobody Sat Dec 27 11:02:25 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1366439FFB for ; Tue, 19 Dec 2023 20:55:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Tue, 19 Dec 2023 12:55:36 -0800 (PST) From: Abel Vesa Date: Tue, 19 Dec 2023 22:55:23 +0200 Subject: [PATCH 2/3] phy: Add PHY Embedded DisplayPort mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231219-x1e80100-phy-edp-compatible-refactor-v1-2-f9e77752953d@linaro.org> References: <20231219-x1e80100-phy-edp-compatible-refactor-v1-0-f9e77752953d@linaro.org> In-Reply-To: <20231219-x1e80100-phy-edp-compatible-refactor-v1-0-f9e77752953d@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Johan Hovold Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=548; i=abel.vesa@linaro.org; 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Signed-off-by: Abel Vesa --- include/linux/phy/phy.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index f6d607ef0e80..bea532711906 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -42,7 +42,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_EDP }; =20 enum phy_media { --=20 2.34.1 From nobody Sat Dec 27 11:02:25 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43EFC3B19E for ; Tue, 19 Dec 2023 20:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Tue, 19 Dec 2023 12:55:38 -0800 (PST) From: Abel Vesa Date: Tue, 19 Dec 2023 22:55:24 +0200 Subject: [PATCH 3/3] phy: qcom: edp: Allow PHY mode configuration via devicetree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231219-x1e80100-phy-edp-compatible-refactor-v1-3-f9e77752953d@linaro.org> References: <20231219-x1e80100-phy-edp-compatible-refactor-v1-0-f9e77752953d@linaro.org> In-Reply-To: <20231219-x1e80100-phy-edp-compatible-refactor-v1-0-f9e77752953d@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Johan Hovold Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Future platforms should not use different compatibles to differentiate between eDP and DP mode. Instead, they should use a single compatible as the IP block is the same, and use the 'phys' (controller) DT property to pass the phy mode. Rework the device match config data so that it only keeps the different knobs rather than swing and pre-emphasis tables. The existing platforms will remain with separate compatibles for each mode. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 89 ++++++++++++++++++++++++++++-----= ---- 1 file changed, 67 insertions(+), 22 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 8e5078304646..c70e6eae16ba 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -68,19 +68,22 @@ =20 #define TXn_TRAN_DRVR_EMP_EN 0x0078 =20 -struct qcom_edp_cfg { - bool is_dp; - - /* DP PHY swing and pre_emphasis tables */ +struct qcom_edp_swing_pre_emph_cfg { const u8 (*swing_hbr_rbr)[4][4]; const u8 (*swing_hbr3_hbr2)[4][4]; const u8 (*pre_emphasis_hbr_rbr)[4][4]; const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; }; =20 +struct qcom_edp_phy_cfg { + int type; + bool needs_swing_pre_emph_cfg; +}; + struct qcom_edp { struct device *dev; - const struct qcom_edp_cfg *cfg; + const struct qcom_edp_phy_cfg *cfg; + const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; =20 struct phy *phy; =20 @@ -96,6 +99,8 @@ struct qcom_edp { =20 struct clk_bulk_data clks[2]; struct regulator_bulk_data supplies[2]; + + bool is_dp; }; =20 static const u8 dp_swing_hbr_rbr[4][4] =3D { @@ -126,8 +131,7 @@ static const u8 dp_pre_emp_hbr2_hbr3[4][4] =3D { { 0x04, 0xff, 0xff, 0xff } }; =20 -static const struct qcom_edp_cfg dp_phy_cfg =3D { - .is_dp =3D true, +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = =3D { .swing_hbr_rbr =3D &dp_swing_hbr_rbr, .swing_hbr3_hbr2 =3D &dp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr =3D &dp_pre_emp_hbr_rbr, @@ -162,18 +166,30 @@ static const u8 edp_pre_emp_hbr2_hbr3[4][4] =3D { { 0x00, 0xff, 0xff, 0xff } }; =20 -static const struct qcom_edp_cfg edp_phy_cfg =3D { - .is_dp =3D false, +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= =3D { .swing_hbr_rbr =3D &edp_swing_hbr_rbr, .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr, .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 +static struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { + .type =3D PHY_TYPE_DP, +}; + +static struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .type =3D PHY_TYPE_DP, + .needs_swing_pre_emph_cfg =3D true, +}; + +static struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { + .type =3D PHY_TYPE_EDP, + .needs_swing_pre_emph_cfg =3D true, +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); - const struct qcom_edp_cfg *cfg =3D edp->cfg; int ret; u8 cfg8; =20 @@ -200,7 +216,7 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - if (cfg && cfg->is_dp) + if (edp->cfg->needs_swing_pre_emph_cfg && edp->is_dp) cfg8 =3D 0xb7; else cfg8 =3D 0x37; @@ -234,7 +250,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_co= nfigure_opts_dp *dp_opts) { - const struct qcom_edp_cfg *cfg =3D edp->cfg; + const struct qcom_edp_swing_pre_emph_cfg *cfg =3D edp->swing_pre_emph_cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; u8 ldo_config; @@ -242,7 +258,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur u8 emph; int i; =20 - if (!cfg) + if (!edp->cfg->needs_swing_pre_emph_cfg) return 0; =20 for (i =3D 0; i < dp_opts->lanes; i++) { @@ -261,7 +277,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur if (swing =3D=3D 0xff || emph =3D=3D 0xff) return -EINVAL; =20 - ldo_config =3D (cfg && cfg->is_dp) ? 0x1 : 0x0; + ldo_config =3D edp->is_dp ? 0x1 : 0x0; =20 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); @@ -447,10 +463,9 @@ static int qcom_edp_set_vco_div(const struct qcom_edp = *edp, unsigned long *pixel static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp =3D phy_get_drvdata(phy); - const struct qcom_edp_cfg *cfg =3D edp->cfg; u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; - u8 ldo_config; + u8 ldo_config =3D 0x0; int timeout; int ret; u32 val; @@ -468,7 +483,8 @@ static int qcom_edp_phy_power_on(struct phy *phy) return timeout; =20 =20 - ldo_config =3D (cfg && cfg->is_dp) ? 0x1 : 0x0; + if (edp->cfg->needs_swing_pre_emph_cfg && edp->is_dp) + ldo_config =3D 0x1; =20 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); @@ -768,6 +784,33 @@ static int qcom_edp_clks_register(struct qcom_edp *edp= , struct device_node *np) return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); } =20 +static struct phy *qcom_edp_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct qcom_edp *edp =3D dev_get_drvdata(dev); + int type =3D edp->cfg->type; + + if (args->args_count =3D=3D 1) + type =3D args->args[0]; + + if (type !=3D PHY_TYPE_DP && type !=3D PHY_TYPE_EDP) + return ERR_PTR(-EINVAL); + + if (type =3D=3D PHY_TYPE_EDP) { + edp->phy->attrs.mode =3D PHY_MODE_EDP; + } else { + edp->phy->attrs.mode =3D PHY_MODE_DP; + edp->is_dp =3D true; + } + + if (edp->cfg->needs_swing_pre_emph_cfg) + edp->swing_pre_emph_cfg =3D edp->is_dp ? + &dp_phy_swing_pre_emph_cfg: + &edp_phy_swing_pre_emph_cfg; + + return edp->phy; +} + static int qcom_edp_phy_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; @@ -832,17 +875,19 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) return PTR_ERR(edp->phy); } =20 + dev_set_drvdata(edp->dev, edp); phy_set_drvdata(edp->phy, edp); =20 - phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + phy_provider =3D devm_of_phy_provider_register(dev, qcom_edp_phy_xlate); + return PTR_ERR_OR_ZERO(phy_provider); } =20 static const struct of_device_id qcom_edp_phy_match_table[] =3D { - { .compatible =3D "qcom,sc7280-edp-phy" }, - { .compatible =3D "qcom,sc8180x-edp-phy" }, - { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &dp_phy_cfg }, - { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &edp_phy_cfg }, + { .compatible =3D "qcom,sc7280-edp-phy" , .data =3D &sc7280_dp_phy_cfg, }, + { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, + { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, + { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &sc8280xp_edp_phy_cf= g, }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table); --=20 2.34.1