From nobody Sat Dec 27 17:05:50 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C845E4B141 for ; Mon, 18 Dec 2023 12:07:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="X/JZ5+5t" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1d307cf18fdso9631665ad.3 for ; Mon, 18 Dec 2023 04:07:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702901252; x=1703506052; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6XGN0l4V5lK+pzpRjICmG52cyuWi32BoHlDHyX2fzxU=; b=X/JZ5+5t7wGTgI6t/+OxK+bCnrEjbDYh148j6MFIBT4ZJKqe/JqMTDp/LurUvzpjLO PlyimPILScrWC0mVot05bo067XHhhmOroZa6zyKbA3efCciNcY5CQJqJgsZ/2tEgXcq3 ijpb8IDQOVg0nnS0TMfce/xEPM+gMXiIbqm2HI0uXfeObd5tMOLIyw744QKdt1+SuHfL WuJZ1PlOaWCXkJ/2tzeIhPeeYQXoAIXEuOeJIADL355UfwuHwW7FYKf/mfOTNStBKrij Ft3jVSjgvpiyMn2+GRo+uyOAGViSdSylodaiJl+v9hiv6bI7RQseYg5ovy8uBuFjJ8x8 nCDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702901252; x=1703506052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6XGN0l4V5lK+pzpRjICmG52cyuWi32BoHlDHyX2fzxU=; b=q7qgA3lAxSa6b6K4V63rAz8mGKdah5Vp9FImpIJWauEPxhm+5Pxatm1ynWnPQAhNw4 hiJkBiQH+z2fBLwLhE4Jvpxe/s+4Jw2KcP7FMpJue40nS0IDokH1hOd7Zct1jZ+s/Q6X wLLcr7wqZgVmaVHwTL2PyWOd1Bn/lK3a60vFN1NN45mUsppOJMk3J/JBlX7eJrhH1I9R O7GQ9XXdYvwljmll/MKZwIXLbWoapRLf7MBAMiQLhQRO1EEIt+9aw0anf/2kLxm1PXMl FFYcdxOP1GXndDr5wWYwwjUmzYI6lIEO8fBlZRECokeruReWI31W6TdkX0YvJZ7o9AWM hFsw== X-Gm-Message-State: AOJu0YxTLJTKBuUJfwigWvou0QyBZtM1b3zkSta5XeCI70e1qh3Qi+7q i7LE1lr7kz+5byz2oMYJAACLb75R6MLuYIGGfA== X-Google-Smtp-Source: AGHT+IHktLh27UF6SwWXcuTMGgrd5PzOnnwJaNZnTznA+SHt8DnQ7XBNQGfcgy37yKImL7SiBzdycw== X-Received: by 2002:a17:902:ce91:b0:1d0:6ffd:ceb7 with SMTP id f17-20020a170902ce9100b001d06ffdceb7mr9928945plg.112.1702901252088; Mon, 18 Dec 2023 04:07:32 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:07:31 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam , Conor Dooley Subject: [PATCH v2 01/16] dt-bindings: phy: qmp-ufs: Fix PHY clocks Date: Mon, 18 Dec 2023 17:36:57 +0530 Message-Id: <20231218120712.16438-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All QMP UFS PHYs except MSM8996 require 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC or TCSR (since SM8550) MSM8996 only requires 'ref' and 'qref' clocks. Hence, fix the binding to reflect the actual clock topology. This change obviously breaks the ABI, but it is inevitable since the clock topology needs to be accurately described in the binding. Reviewed-by: Conor Dooley Signed-off-by: Manivannan Sadhasivam --- .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 47 +++++++++---------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.ya= ml index f3a3296c811c..800f11b29dcd 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -37,15 +37,12 @@ properties: maxItems: 1 =20 clocks: - minItems: 1 + minItems: 2 maxItems: 3 =20 clock-names: - minItems: 1 - items: - - const: ref - - const: ref_aux - - const: qref + minItems: 2 + maxItems: 3 =20 power-domains: maxItems: 1 @@ -85,22 +82,9 @@ allOf: compatible: contains: enum: + - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy - qcom,sc7280-qmp-ufs-phy - - qcom,sm8450-qmp-ufs-phy - then: - properties: - clocks: - minItems: 3 - clock-names: - minItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy - qcom,sdm845-qmp-ufs-phy @@ -111,13 +95,18 @@ allOf: - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy - qcom,sm8350-qmp-ufs-phy + - qcom,sm8450-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy then: properties: clocks: - maxItems: 2 + minItems: 3 + maxItems: 3 clock-names: - maxItems: 2 + items: + - const: ref + - const: ref_aux + - const: qref =20 - if: properties: @@ -128,22 +117,28 @@ allOf: then: properties: clocks: - maxItems: 1 + minItems: 2 + maxItems: 2 clock-names: - maxItems: 1 + items: + - const: ref + - const: qref =20 additionalProperties: false =20 examples: - | #include + #include =20 ufs_mem_phy: phy@1d87000 { compatible =3D "qcom,sc8280xp-qmp-ufs-phy"; reg =3D <0x01d87000 0x1000>; =20 - clocks =3D <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AU= X_CLK>; - clock-names =3D "ref", "ref_aux"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_REF_CLKREF_CLK>; + + clock-names =3D "ref", "ref_aux", "qref"; =20 power-domains =3D <&gcc UFS_PHY_GDSC>; =20 --=20 2.25.1 From nobody Sat Dec 27 17:05:50 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C1A94B156 for ; Mon, 18 Dec 2023 12:07:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="c4ZY/aRa" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1d045097b4cso9771075ad.0 for ; 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charset="utf-8" Device drivers should just rely on the clocks provided by the devicetree and enable/disable them based on the requirement. There is no need to validate the clocks provided by devicetree in the driver. That's the job of DT schema. So let's switch to devm_clk_bulk_get_all() API that just gets the clocks provided by devicetree and remove hardcoded clocks info. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 61 +++---------------------- 1 file changed, 7 insertions(+), 54 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 514fa14df634..174b105fda82 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -837,9 +837,6 @@ struct qmp_phy_cfg { /* Additional sequence for HS G4 */ const struct qmp_phy_cfg_tbls tbls_hs_g4; =20 - /* clock ids to be requested */ - const char * const *clk_list; - int num_clks; /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -865,6 +862,7 @@ struct qmp_ufs { void __iomem *rx2; =20 struct clk_bulk_data *clks; + int num_clks; struct regulator_bulk_data *vregs; struct reset_control *ufs_reset; =20 @@ -897,20 +895,6 @@ static inline void qphy_clrbits(void __iomem *base, u3= 2 offset, u32 val) readl(base + offset); } =20 -/* list of clocks required by phy */ -static const char * const msm8996_ufs_phy_clk_l[] =3D { - "ref", -}; - -/* the primary usb3 phy on sm8250 doesn't have a ref clock */ -static const char * const sm8450_ufs_phy_clk_l[] =3D { - "qref", "ref", "ref_aux", -}; - -static const char * const sdm845_ufs_phy_clk_l[] =3D { - "ref", "ref_aux", -}; - /* list of regulators */ static const char * const qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", @@ -948,9 +932,6 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), }, =20 - .clk_list =3D msm8996_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), - .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -986,8 +967,6 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sm8450_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1020,8 +999,6 @@ static const struct qmp_phy_cfg sc7280_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), }, - .clk_list =3D sm8450_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v4_regs_layout, @@ -1054,8 +1031,6 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1080,8 +1055,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { .serdes =3D sdm845_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v3_regs_layout, @@ -1108,8 +1081,6 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { .serdes =3D sm6115_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v2_regs_layout, @@ -1136,8 +1107,6 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg =3D= { .serdes =3D sdm845_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v3_regs_layout, @@ -1172,8 +1141,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { .pcs =3D sm8150_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v4_regs_layout, @@ -1206,8 +1173,6 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D= { .pcs =3D sm8150_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v4_regs_layout, @@ -1240,8 +1205,6 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1274,8 +1237,6 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D= { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sm8450_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1296,8 +1257,6 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg =3D= { .pcs =3D sm8550_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8550_ufsphy_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v6_regs_layout, @@ -1383,7 +1342,7 @@ static int qmp_ufs_com_init(struct qmp_ufs *qmp) return ret; } =20 - ret =3D clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + ret =3D clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); if (ret) goto err_disable_regulators; =20 @@ -1403,7 +1362,7 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) =20 reset_control_assert(qmp->ufs_reset); =20 - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -1573,19 +1532,13 @@ static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) =20 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; struct device *dev =3D qmp->dev; - int num =3D cfg->num_clks; - int i; =20 - qmp->clks =3D devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); - if (!qmp->clks) - return -ENOMEM; + qmp->num_clks =3D devm_clk_bulk_get_all(dev, &qmp->clks); + if (qmp->num_clks < 0) + return qmp->num_clks; =20 - for (i =3D 0; i < num; i++) - qmp->clks[i].id =3D cfg->clk_list[i]; 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Mon, 18 Dec 2023 04:07:43 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:07:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 03/16] dt-bindings: clock: qcom: Add missing UFS QREF clocks Date: Mon, 18 Dec 2023 17:36:59 +0530 Message-Id: <20231218120712.16438-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 0fadcdfdcf57 ("dt-bindings: clock: Add SC8180x GCC binding") Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-sc8180x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bind= ings/clock/qcom,gcc-sc8180x.h index e893415ae13d..90c6e021a035 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -246,6 +246,8 @@ #define GCC_PCIE_3_CLKREF_CLK 236 #define GCC_USB3_PRIM_CLKREF_CLK 237 #define GCC_USB3_SEC_CLKREF_CLK 238 +#define GCC_UFS_MEM_CLKREF_EN 239 +#define GCC_UFS_CARD_CLKREF_EN 240 =20 #define GCC_EMAC_BCR 0 #define GCC_GPU_BCR 1 --=20 2.25.1 From nobody Sat Dec 27 17:05:50 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDDD14CB32 for ; Mon, 18 Dec 2023 12:07:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wa7g6UoM" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1d3c76ee799so1936195ad.3 for ; Mon, 18 Dec 2023 04:07:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702901269; x=1703506069; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1DxFXPJYgIG7bY+rEjLLq6eWKt7yGgrHuHLxSAUgD04=; b=wa7g6UoM4wbtaeBA39IPuyEx74DiXYc7UKKLrxC0mOxbc0PJ/QT6Rc6Wmz6vdmqBz/ yVy9MP9qcaiMenn8S9OvuRfKP9fiyXhAfOt9L3HFnYwaMq98XK2seHGrQQWZteuoekGB bT7qfZeWTaZ9bslOFZvGBAXPKrDM7QsAaBbeAS14h+baHvpdCOnNVL36VBkyIr7NcEfJ 6ufAuJ/Zr10qf1EVdGGXql3DVRgJE6iV2Cx8f6B1Meo7O/fJocSZYw/TxWI/qRrFJKFq 9yg5OJew0FjK5L3EfE8rK9LQ5o5q1dtL2KFC1gDouNIBjXC0lf2oPtUNe8gAWbVbjIgo Smqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702901269; x=1703506069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1DxFXPJYgIG7bY+rEjLLq6eWKt7yGgrHuHLxSAUgD04=; b=ZJyPNVih0oPHsNvhNaLl1LpnycAGBeVqO3OkXGNsHeX/ssPHt1YkpSgZw76zSlnJ9m IsaDkU5Sk6pyI7rVCwbmMUkLG4OrdL9Od1GSdICfRHyIlJ2XXJKdVASXidc5nNry2mL+ U5qUuPa35I3RGoUpzTei3na6pcjOlWXdtBMf9VE0xlH2PP7BkYnmO5ToWE4ShtFHUvBE 2i8XaUXWUa2qxLaBy9jJXs3BsyCEIeosI76OFKNxRvy+YouiajmVaRwrYN0WPjdZOfmJ +0mveTmHl2PmljC8BXab8y1ED31KBx2d4CCQtNqm5zLB0FqLrDpAEZfZBMKWQTMK+TlV DOqg== X-Gm-Message-State: AOJu0Yzjpyhmg10H//z4vy9I5D8+fDGPC9o/HsO/phEJ9KtutWPOeb/n gDFsKU3aFvWu89XWIWC39Knf X-Google-Smtp-Source: AGHT+IEK1evDaORIVdgFmQY6oqeCQ/c/a7zO1rPGBojethcXGGLrT6jJIMMz7NCm2ipjlMCXMK2xiA== X-Received: by 2002:a17:903:110e:b0:1d3:1773:8555 with SMTP id n14-20020a170903110e00b001d317738555mr5851554plh.115.1702901269314; Mon, 18 Dec 2023 04:07:49 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:07:48 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 04/16] clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks Date: Mon, 18 Dec 2023 17:37:00 +0530 Message-Id: <20231218120712.16438-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver fo= r SC8180x") Signed-off-by: Manivannan Sadhasivam Acked-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index ae2147381559..544567db45f1 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_= clk =3D { }, }; =20 +static struct clk_branch gcc_ufs_card_clkref_en =3D { + .halt_reg =3D 0x8c004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_card_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_card_ahb_clk =3D { .halt_reg =3D 0x75014, .halt_check =3D BRANCH_HALT, @@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw= _ctl_clk =3D { }, }; =20 +static struct clk_branch gcc_ufs_mem_clkref_en =3D { + .halt_reg =3D 0x8c000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_mem_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_ahb_clk =3D { .halt_reg =3D 0x77014, .halt_check =3D BRANCH_HALT, @@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] =3D { [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] =3D &gcc_ufs_card_2_tx_symbol_0_clk.clkr, [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] =3D &gcc_ufs_card_2_unipro_core_clk.clkr, [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] =3D &gcc_ufs_card_2_unipro_core_clk_= src.clkr, + [GCC_UFS_CARD_CLKREF_EN] =3D &gcc_ufs_card_clkref_en.clkr, [GCC_UFS_CARD_AHB_CLK] =3D &gcc_ufs_card_ahb_clk.clkr, [GCC_UFS_CARD_AXI_CLK] =3D &gcc_ufs_card_axi_clk.clkr, [GCC_UFS_CARD_AXI_CLK_SRC] =3D &gcc_ufs_card_axi_clk_src.clkr, @@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] =3D { [GCC_UFS_CARD_UNIPRO_CORE_CLK] =3D &gcc_ufs_card_unipro_core_clk.clkr, [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =3D &gcc_ufs_card_unipro_core_clk_src.= clkr, [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =3D &gcc_ufs_card_unipro_core_hw_ct= l_clk.clkr, + [GCC_UFS_MEM_CLKREF_EN] =3D &gcc_ufs_mem_clkref_en.clkr, [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, --=20 2.25.1 From nobody Sat Dec 27 17:05:50 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6AFD4D5B5 for ; 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Mon, 18 Dec 2023 04:07:54 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 05/16] arm64: dts: qcom: msm8996: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:01 +0530 Message-Id: <20231218120712.16438-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in MSM8996 requires 2 clocks: * ref - 19.2MHz reference clock from RPM * qref - QREF clock from GCC Fixes: 27520210e881 ("arm64: dts: qcom: msm8996: Use generic QMP driver for= UFS") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index 6ba9da9e6a8b..b235f1d651aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2105,8 +2105,8 @@ ufsphy: phy@627000 { #size-cells =3D <1>; ranges; =20 - clocks =3D <&gcc GCC_UFS_CLKREF_CLK>; - clock-names =3D "ref"; + clocks =3D <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; + clock-names =3D "ref", "qref"; =20 resets =3D <&ufshc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:50 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF63F4EB52 for ; Mon, 18 Dec 2023 12:08:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ODfaBI6M" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1d3ad3ad517so2511595ad.0 for ; Mon, 18 Dec 2023 04:08:01 -0800 (PST) DKIM-Signature: v=1; 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Mon, 18 Dec 2023 04:08:01 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:08:00 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 06/16] arm64: dts: qcom: msm8998: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:02 +0530 Message-Id: <20231218120712.16438-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in MSM8998 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: cd3dbe2a4e6c ("arm64: dts: qcom: msm8998: Add UFS nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index b6a3e6afaefd..d4c55e2b0043 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1051,12 +1051,12 @@ ufsphy: phy@1da7000 { status =3D "disabled"; ranges; =20 - clock-names =3D - "ref", - "ref_aux"; - clocks =3D - <&gcc GCC_UFS_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_AUX_CLK>; + clocks =3D <&rpmcc RPM_SMD_LN_BB_CLK1>, + <&gcc GCC_UFS_PHY_AUX_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + clock-names =3D "ref", + "ref_aux", + "qref"; =20 reset-names =3D "ufsphy"; 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Mon, 18 Dec 2023 04:08:07 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:08:06 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 07/16] arm64: dts: qcom: sdm845: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:03 +0530 Message-Id: <20231218120712.16438-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SDM845 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: cc16687fbd74 ("arm64: dts: qcom: sdm845: add UFS controller") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index cb3bfd262851..a7529af5bc6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2619,10 +2619,12 @@ ufs_mem_phy: phy@1d87000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names =3D "ref", - "ref_aux"; - clocks =3D <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; =20 resets =3D <&ufs_mem_hc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:50 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3BFF4F1F3 for ; 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Mon, 18 Dec 2023 04:08:12 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 08/16] arm64: dts: qcom: sm6115: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:04 +0530 Message-Id: <20231218120712.16438-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SM6115 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index 839c60351240..40394c412fdf 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1033,8 +1033,12 @@ ufs_mem_phy: phy@4807000 { #size-cells =3D <2>; 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charset="utf-8" QMP PHY used in SM6125 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: f8399e8a2f80 ("arm64: dts: qcom: sm6125: Add UFS nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index eb07eca3a48d..b46d3c1fa47a 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -812,10 +812,12 @@ ufs_mem_phy: phy@4807000 { compatible =3D "qcom,sm6125-qmp-ufs-phy"; reg =3D <0x04807000 0xdb8>; =20 - clocks =3D <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names =3D "ref", - "ref_aux"; + "ref_aux", + "qref"; =20 resets =3D <&ufs_mem_hc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:51 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7C104F8B3 for ; Mon, 18 Dec 2023 12:08:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TORj6iqH" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1d3470496e2so26074235ad.1 for ; Mon, 18 Dec 2023 04:08:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702901305; x=1703506105; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Mon, 18 Dec 2023 04:08:25 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:08:24 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 10/16] arm64: dts: qcom: sm6350: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:06 +0530 Message-Id: <20231218120712.16438-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SM6350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 5a814af5fc22 ("arm64: dts: qcom: sm6350: Add UFS nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 8fd6f4d03490..ef793d48316d 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1192,10 +1192,12 @@ ufs_mem_phy: phy@1d87000 { #size-cells =3D <2>; ranges; =20 + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names =3D "ref", - "ref_aux"; - clocks =3D <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; =20 resets =3D <&ufs_mem_hc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:51 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85D694F8A2 for ; Mon, 18 Dec 2023 12:08:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sHwZmpec" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1d045097b4cso9776765ad.0 for ; Mon, 18 Dec 2023 04:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702901311; x=1703506111; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+NpBpw87ancReoayxiYNLEpdh+qbLyvkQJUBfcAOaoQ=; b=sHwZmpeco/gTdT87jm1yr3TGjh2hS48sfxvc++zpJ7ghQlVNZIGELUijwlisT42vCd zLmeUQWbzVWiy92b9XS7CAGG7tyNceeWGEO0C6LYA6GjPKCsZik4nTzEVCZaPOtB1XjN Dgh2Ngxzhl7A/Yc+w9qegYozV7nuSSzULKaSTDS3x8aRxhnOyK2ZMbhA/k1zvDUS18vh 98Kza6Gr0mrn7gkESuRaV0Xbvm/EN7kxr6aYB+xoSk9UpCI55Nw9LeSoAWOzJNGQm29F ZFQNyOnOZLUwFBmAZ7w+BzbSAPmHpEkgMxagJsduwC+k57f33jRCOpMnfXbalYEgqj5W 5svg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702901311; x=1703506111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+NpBpw87ancReoayxiYNLEpdh+qbLyvkQJUBfcAOaoQ=; b=LVgngJOaiRrpoRCcm3qBJ/SP0ifqSRdkzs0miOj3qWH+xaH2rVeQek5niEocStQulO 4lSOlyCsudZiKq7tqTLOxR+kqkxGdykzUNBS8+53njjDYxxK7Y70GAnmu+BbJUGmLcKq L0Ud7bBTRW57R7+NdZyDft9dt+xGjzc1VNUzqWAae3dY5XWFpwQZ1N3GdDbMdudREig7 1P/MoQnXI2tqgmEXK/xyX9Y8nPgm0MvUARnqlEOgSPqZC6yHR5qxAYnIcio9+8uSv3vo 6Ur+dzLYMBED5wGW7CeMKvs98agjMHvWXsBk1iChaCi1oqx9MIZ0BnioFx3eYhR49l5U tCNA== X-Gm-Message-State: AOJu0YzWQmmYcJcUF1Iqki/h8pIAiz1klEpYLJPwyh7dPiG42Bqx8E0u +pJ1kpzDBckz2R6lVpp0RQMw X-Google-Smtp-Source: AGHT+IHWUgQYCUGlqwV406h6zHwdKzU4NG59nQYN4sJQ2Em0W4gzvKZvabKGPJlQn2udUzFH5dAm9g== X-Received: by 2002:a17:903:1106:b0:1d3:aab1:6273 with SMTP id n6-20020a170903110600b001d3aab16273mr870341plh.118.1702901310948; Mon, 18 Dec 2023 04:08:30 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:08:30 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 11/16] arm64: dts: qcom: sm8150: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:07 +0530 Message-Id: <20231218120712.16438-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SM8150 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 3834a2e92229 ("arm64: dts: qcom: sm8150: Add ufs nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 43d56968a382..18af94852974 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2065,10 +2065,12 @@ ufs_mem_phy: phy@1d87000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names =3D "ref", - "ref_aux"; - clocks =3D <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; =20 power-domains =3D <&gcc UFS_PHY_GDSC>; =20 --=20 2.25.1 From nobody Sat Dec 27 17:05:51 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99EBC50278 for ; Mon, 18 Dec 2023 12:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OaeZBgGI" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-1d39e2f1089so14204795ad.1 for ; Mon, 18 Dec 2023 04:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702901317; x=1703506117; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gvNQvdCy0O2wlOymvN0iIUEpRjoZ42RcAo4vagPpclg=; b=OaeZBgGId48TKNSt68mRweEao0G3RMcTDyEpl+QCMugxwzi8t6tusUauc/p3xkAoBS GJrdH/aax9MQE7DgFYRKJkAsHP4cNIYx3183Blg8/uvd4hJ2YCSZbczf83o/+Z6cadL/ N5Ic5YbPIrUVggaxTbE+gyBb6d3gmg5Qhrbjz764t8DLhxAy3BuJurowLR9vznFUp9iB Bdi/yWxlcNXEaz2sqR8TkcfdmS7qG3shAeknLUW16G0sme0zbvpAkWW6sLhV7pkEfgZa HfOiqpYIFZVIR7jONwCZcB0AzsgR22WurWk0FsWMMNE75TamxeNRjbbqn7mvu9yU3Wux hs1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702901317; x=1703506117; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gvNQvdCy0O2wlOymvN0iIUEpRjoZ42RcAo4vagPpclg=; b=J3eUqMRluNbfrG+KMABR9Ng7uKXzOeDSNHT6lkXxLgJ0mNF5YsinBUXGDZIQRLJ/3e TUgeiS/xO4JiT9uLq1Iph/ArQRJNAVHq5pQva/bePQHLmFBBKVsfj85ctlHlA7k3q2gE /SWIPvIU1fYjOMm7+rRZL+XhmuGaSw2XwrXYpngG1GiVLyE3/yl4CiZPJRTGqUtznIDz 2WaRMkfkTSlaWUs0wkuU83YG91oPMhQZGpDONmQmIfA4LxB9/p0FFHzRPU5CpCbWMr/3 EyVxr1V2DGwzou+C18MM3r2Q6dfTaO/90JZmsnIMVYhDxWk3Zjk8UQAcMgwmOXChQDmO Qpcg== X-Gm-Message-State: AOJu0YydRT5t4UgnNXofvSX3VaBylC7e86TOMsmuFEOgKbALPEEMWf8g lR30C3Lf7q+UzRLEvdoOqntZ X-Google-Smtp-Source: AGHT+IEmFgwhty4eOC1HWIN6R/wmWkUmpHUAMlQfWfME+fkRcMzo7kKJtBRaeLQkaRQozYVIufi4aw== X-Received: by 2002:a17:903:24c:b0:1d0:6ffd:9e1e with SMTP id j12-20020a170903024c00b001d06ffd9e1emr18461127plh.112.1702901316940; Mon, 18 Dec 2023 04:08:36 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:08:36 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 12/16] arm64: dts: qcom: sm8250: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:08 +0530 Message-Id: <20231218120712.16438-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SM8250 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: b7e2fba06622 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index c1b7f9620ec6..e47c515af6cf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2486,10 +2486,12 @@ ufs_mem_phy: phy@1d87000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; - clock-names =3D "ref", - "ref_aux"; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1X_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; =20 resets =3D <&ufs_mem_hc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:51 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A713524CB for ; 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Mon, 18 Dec 2023 04:08:42 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 13/16] arm64: dts: qcom: sc8180x: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:09 +0530 Message-Id: <20231218120712.16438-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SC8180X requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 8bcc8c0bb0d0..5591e147bde1 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2122,9 +2122,11 @@ ufs_mem_phy: phy-wrapper@1d87000 { reg =3D <0 0x01d87000 0 0x1000>; =20 clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_EN>; clock-names =3D "ref", - "ref_aux"; + "ref_aux", + "qref"; =20 resets =3D <&ufs_mem_hc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:51 2025 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F05851026 for ; Mon, 18 Dec 2023 12:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KizIXyRJ" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1d3470496e2so26077765ad.1 for ; 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charset="utf-8" QMP PHY used in SC8280XP requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index cad59af7ccef..37344abbe8bf 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2256,9 +2256,12 @@ ufs_mem_phy: phy@1d87000 { compatible =3D "qcom,sc8280xp-qmp-ufs-phy"; reg =3D <0 0x01d87000 0 0x1000>; =20 - clocks =3D <&gcc GCC_UFS_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names =3D "ref", "ref_aux"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_CARD_CLKREF_CLK>; + clock-names =3D "ref", + "ref_aux", + "qref"; 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Mon, 18 Dec 2023 04:08:54 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 15/16] arm64: dts: qcom: sm8350: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:11 +0530 Message-Id: <20231218120712.16438-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SM8350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index f4b8439200f5..38a09d71b3e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1727,10 +1727,12 @@ ufs_mem_phy: phy@1d87000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges; - clock-names =3D "ref", - "ref_aux"; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; =20 resets =3D <&ufs_mem_hc 0>; reset-names =3D "ufsphy"; --=20 2.25.1 From nobody Sat Dec 27 17:05:51 2025 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 603175731E for ; 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Mon, 18 Dec 2023 04:09:00 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 16/16] arm64: dts: qcom: sm8550: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:12 +0530 Message-Id: <20231218120712.16438-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QMP PHY used in SM8550 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from TCSR Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and= phy nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Can Guo Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index baa8540868a4..386ffd0d72c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1891,9 +1891,12 @@ crypto: crypto@1dfa000 { ufs_mem_phy: phy@1d80000 { compatible =3D "qcom,sm8550-qmp-ufs-phy"; reg =3D <0x0 0x01d80000 0x0 0x2000>; - clocks =3D <&tcsr TCSR_UFS_CLKREF_EN>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names =3D "ref", "ref_aux"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; =20 power-domains =3D <&gcc UFS_MEM_PHY_GDSC>; =20 --=20 2.25.1