From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBE941BDD1; Mon, 18 Dec 2023 11:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="nhv/Eihf" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id A0B932D0186A; Mon, 18 Dec 2023 12:39:54 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id Mx8Z8RHDthnf; Mon, 18 Dec 2023 12:39:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 1E5EF2D01869; Mon, 18 Dec 2023 12:39:54 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl 1E5EF2D01869 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899594; bh=N759/7W2UuYqap0Ll6FWIgn4ZQx1EOVZZXI1tKKVL24=; h=From:To:Date:Message-Id:MIME-Version; b=nhv/EihfS9XbQbOuV6Jyd1Q2lrlMmzLi+/pMh7D22+lL+YmXE1E2fi9x4kZFSURQV 6e61W+oSCZK8nXPumaL1zpoS6efeG56Z7B6JSKISKLNe7Be0xdliZ5OameqhSKQjwq Qde9XEnqlc5oHdEWeZxD3rwxtG3Myg38L/2FyaNgX3rjJ+XSzC+3xvlo2sFhK3fdfQ JN5AWv0cbznMEIp7nRpv8aPRO5l97ktlQkvbcJkONUrwuCo/vUIWUxBEGGl7wRaD/g OcBphnHZyjI566luw3JdZVfxXOu+OVZVr5jtSbkxwlAC4Asao8srl3g0Y73bP1yKgh NFvI+2UUqyfzA== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id xLBxOmbdUng6; Mon, 18 Dec 2023 12:39:54 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id D04F72D01868; Mon, 18 Dec 2023 12:39:53 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 1/8] dmaengine: xilinx: xdma: Get rid of unused code Date: Mon, 18 Dec 2023 12:39:36 +0100 Message-Id: <20231218113943.9099-2-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get rid of duplicated macro definitions, as these macros are defined earlier in the file. Also, get rid of unused member of 'struct xdma_desc'. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma-regs.h | 12 ------------ drivers/dma/xilinx/xdma.c | 2 -- 2 files changed, 14 deletions(-) diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h index e641a5083e14..0b17a931f583 100644 --- a/drivers/dma/xilinx/xdma-regs.h +++ b/drivers/dma/xilinx/xdma-regs.h @@ -134,18 +134,6 @@ struct xdma_hw_desc { #define XDMA_SGDMA_DESC_ADJ 0x4088 #define XDMA_SGDMA_DESC_CREDIT 0x408c =20 -/* bits of the SG DMA control register */ -#define XDMA_CTRL_RUN_STOP BIT(0) -#define XDMA_CTRL_IE_DESC_STOPPED BIT(1) -#define XDMA_CTRL_IE_DESC_COMPLETED BIT(2) -#define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3) -#define XDMA_CTRL_IE_MAGIC_STOPPED BIT(4) -#define XDMA_CTRL_IE_IDLE_STOPPED BIT(6) -#define XDMA_CTRL_IE_READ_ERROR GENMASK(13, 9) -#define XDMA_CTRL_IE_DESC_ERROR GENMASK(23, 19) -#define XDMA_CTRL_NON_INCR_ADDR BIT(25) -#define XDMA_CTRL_POLL_MODE_WB BIT(26) - /* * interrupt registers */ diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 290bb5d2d1e2..ddb9e7d07461 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -78,7 +78,6 @@ struct xdma_chan { * @vdesc: Virtual DMA descriptor * @chan: DMA channel pointer * @dir: Transferring direction of the request - * @dev_addr: Physical address on DMA device side * @desc_blocks: Hardware descriptor blocks * @dblk_num: Number of hardware descriptor blocks * @desc_num: Number of hardware descriptors @@ -91,7 +90,6 @@ struct xdma_desc { struct virt_dma_desc vdesc; struct xdma_chan *chan; enum dma_transfer_direction dir; - u64 dev_addr; struct xdma_desc_block *desc_blocks; u32 dblk_num; u32 desc_num; --=20 2.34.1 From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 592451C69F; Mon, 18 Dec 2023 11:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="OGj7rcHG" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 55DF12D0186B; Mon, 18 Dec 2023 12:40:08 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id h2uf9FnBVTbJ; Mon, 18 Dec 2023 12:40:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 8DFDD2D0186A; Mon, 18 Dec 2023 12:40:07 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl 8DFDD2D0186A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899607; bh=FEcsprV3vVBU8tN4mn0OPH95yCWNxfshZ/vGB2JO2Kw=; h=From:To:Date:Message-Id:MIME-Version; b=OGj7rcHGESqG9XzXgjYZD6jqmhYxRGOTQHxns6/982zBeI6o49VexBzr5jne8dlLm L2bxKzhVAC2AG9NPQbq8qqOo9a7TJC3JITt+bHk6gZIwuD8KzEwzsmYZFk69IqsFwA TPJ762Poiu9TQdkX7CAP44dE3zfVF8JkKmlfuYGidA/M3EVmfwlZi6KrLUnDx4GKBp 1Bw1516M1v29DdH5r5ZDFbW28gP0LThp6870CjTTzcD7Tu0wO+3/7lyHqFgCCRzNet 6gtZ1lCdqREUb8yfxFi5UILpQwgS9gSdfJ6d9G+Vo989UP8/VHtFjlFCe5/y+SOFqo LB9tzehhKWjlQ== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id 7pxWRintu_tT; Mon, 18 Dec 2023 12:40:07 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 021F82D01868; Mon, 18 Dec 2023 12:40:06 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 2/8] dmaengine: xilinx: xdma: Add necessary macro definitions Date: Mon, 18 Dec 2023 12:39:37 +0100 Message-Id: <20231218113943.9099-3-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Complete lacking bits describing the status/control register values. Add macros describing the status/control registers. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma-regs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h index 0b17a931f583..98117e8a466f 100644 --- a/drivers/dma/xilinx/xdma-regs.h +++ b/drivers/dma/xilinx/xdma-regs.h @@ -76,6 +76,7 @@ struct xdma_hw_desc { #define XDMA_CHAN_CONTROL_W1S 0x8 #define XDMA_CHAN_CONTROL_W1C 0xc #define XDMA_CHAN_STATUS 0x40 +#define XDMA_CHAN_STATUS_RC 0x44 #define XDMA_CHAN_COMPLETED_DESC 0x48 #define XDMA_CHAN_ALIGNMENTS 0x4c #define XDMA_CHAN_INTR_ENABLE 0x90 @@ -101,6 +102,7 @@ struct xdma_hw_desc { #define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4) #define CHAN_CTRL_IE_IDLE_STOPPED BIT(6) #define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9) +#define CHAN_CTRL_IE_WRITE_ERROR GENMASK(18, 14) #define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19) #define CHAN_CTRL_NON_INCR_ADDR BIT(25) #define CHAN_CTRL_POLL_MODE_WB BIT(26) @@ -111,8 +113,17 @@ struct xdma_hw_desc { CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \ CHAN_CTRL_IE_MAGIC_STOPPED | \ CHAN_CTRL_IE_READ_ERROR | \ + CHAN_CTRL_IE_WRITE_ERROR | \ CHAN_CTRL_IE_DESC_ERROR) =20 +#define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START + +#define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \ + CHAN_CTRL_IE_MAGIC_STOPPED | \ + CHAN_CTRL_IE_READ_ERROR | \ + CHAN_CTRL_IE_WRITE_ERROR | \ + CHAN_CTRL_IE_DESC_ERROR) + /* bits of the channel interrupt enable mask */ #define CHAN_IM_DESC_ERROR BIT(19) #define CHAN_IM_READ_ERROR BIT(9) --=20 2.34.1 From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1223B39FFB; Mon, 18 Dec 2023 11:40:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="MyOOARhx" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id CB0B62D0186C; Mon, 18 Dec 2023 12:40:16 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id bDdscBx1haka; Mon, 18 Dec 2023 12:40:15 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id CB3CE2D0186B; Mon, 18 Dec 2023 12:40:15 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl CB3CE2D0186B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899615; bh=kigQbZ6cbWkglz4+/r5I9p25DVWVAlGCZgXXB8MiuAQ=; h=From:To:Date:Message-Id:MIME-Version; b=MyOOARhx2Yc9lzdHbbxlIeqh+8y3DqM/cAPrBvNuEbF+Db5WH45B/jZyLnum+k0P4 93MUfFZW49jgbw59ZfpZizEbmTxXOn1yWsUsXDE37D9fEipK8rclvZyLvISTiYN2jr 6AdXMRLBH0Kl/KCOj2XfCXZ9Guk4+Xq+kGsWv0nzi0oVIEfk5rvEicZOzFRsM+0cPv +InC1ZK9pP2bpMFHppXO1tgct68zEPTcdhTOUiX3idwrf591cWX/r8BgW6LYCmjVMO 0Wa3d+aIsZcBkCTuxW0lBvadisPbHykmkjaVJLfNLOW8dRswsH6AQyi4TspTUB3hiy Lbdjos4raJMFw== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id Z4XuabPfu1Xz; Mon, 18 Dec 2023 12:40:15 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 75E422D01868; Mon, 18 Dec 2023 12:40:15 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 3/8] dmaengine: xilinx: xdma: Ease dma_pool alignment requirements Date: Mon, 18 Dec 2023 12:39:38 +0100 Message-Id: <20231218113943.9099-4-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the XDMA datasheet (PG195), the address of any descriptor must be 32 byte aligned. The datasheet also states that a contiguous block of descriptors must not cross a 4k address boundary. Therefore, it is possible to ease the pressure put on the dma_pool allocator just by requiring sufficient alignment and boundary values. Add proper macro definition and change the values passed into the dma_pool_create(). Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma-regs.h | 7 ++++--- drivers/dma/xilinx/xdma.c | 5 ++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h index 98117e8a466f..98f5f6fb9ff9 100644 --- a/drivers/dma/xilinx/xdma-regs.h +++ b/drivers/dma/xilinx/xdma-regs.h @@ -64,9 +64,10 @@ struct xdma_hw_desc { __le64 next_desc; }; =20 -#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc) -#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT) -#define XDMA_DESC_BLOCK_ALIGN 4096 +#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc) +#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT) +#define XDMA_DESC_BLOCK_ALIGN 32 +#define XDMA_DESC_BLOCK_BOUNDARY 4096 =20 /* * Channel registers diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index ddb9e7d07461..c22701e76b69 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -741,9 +741,8 @@ static int xdma_alloc_chan_resources(struct dma_chan *c= han) return -EINVAL; } =20 - xdma_chan->desc_pool =3D dma_pool_create(dma_chan_name(chan), - dev, XDMA_DESC_BLOCK_SIZE, - XDMA_DESC_BLOCK_ALIGN, 0); + xdma_chan->desc_pool =3D dma_pool_create(dma_chan_name(chan), dev, XDMA_D= ESC_BLOCK_SIZE, + XDMA_DESC_BLOCK_ALIGN, XDMA_DESC_BLOCK_BOUNDARY); if (!xdma_chan->desc_pool) { xdma_err(xdev, "unable to allocate descriptor pool"); return -ENOMEM; --=20 2.34.1 From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4073C3B297; Mon, 18 Dec 2023 11:40:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="FWxYioBt" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 0B13A2D0186E; Mon, 18 Dec 2023 12:40:22 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id VGIWlgQFWWGy; Mon, 18 Dec 2023 12:40:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id AC2D22D0186B; Mon, 18 Dec 2023 12:40:21 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl AC2D22D0186B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899621; bh=C6InQ+4d15iDKyNcFXHPVTUZ8feoM5yp2MCadEFmw+g=; h=From:To:Date:Message-Id:MIME-Version; b=FWxYioBtV+CuN4ZKXhsYKHaP1DEtyZoHbu0sQIka9w4vbLzIaIWQXW0XVWNm1P/nv 1/fhDgEi/C4Klm0ydTBuc0pKQToG88PHP1FjJm39JVH4Vufk7ZS6stkDzKllMpuqTh l3Vu5lBmDhKEZoEA5AFx3FMOoG5Nd6aEk1NNTd4A5FxMO4cNC+wkrYYu2Ws3L2tPNC zMiiroszXMqoHHMhLHsZOWGQJkogvmFLnCWC7f9t2bVsVjJlyrvqQDGM0XKKz9vWGr Hzf677yCa5sJf5ZUpn7vA7wefwf+SX7wusmZxNNVNWo0UzmdwXQckusOUTXRJ346vB MlBkucwOEiqeg== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id UDKqkfsa-b3i; Mon, 18 Dec 2023 12:40:21 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 7827E2D01868; Mon, 18 Dec 2023 12:40:21 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 4/8] dmaengine: xilinx: xdma: Rework xdma_terminate_all() Date: Mon, 18 Dec 2023 12:39:39 +0100 Message-Id: <20231218113943.9099-5-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify xdma_xfer_stop(). Stop the dma engine and clear its status register unconditionally - just do what its name states. This change also allows to call it without grabbing a lock, which minimizes the total time spent with a spinlock held. Delete the currently processed vd.node from the vc.desc_issued list prior to passing it to vchan_terminate_vdesc(). In case there's more than one descriptor pending on vc.desc_issued list, calling vchan_terminate_desc() results in losing the link between vc.desc_issued list head and the second descriptor on the list. Doing so results in resources leakege, as vchan_dma_desc_free_list() won't be able to properly free memory resources attached to descriptors, resulting in dma_pool_destroy() failure. Don't call vchan_dma_desc_free_list() from within xdma_terminate_all(). Move all terminated descriptors to the vc.desc_terminated list instead. This allows to postpone freeing memory resources associated with descriptors until the call to vchan_synchronize(), which is called from xdma_synchronize() callback. This is the right way to do it - xdma_terminate_all() should return as soon as possible, while freeing resources (that may be time consuming in case of large number of descriptors) can be done safely later. Fixes: 49a701d8dc1e ("dmaengine: xilinx: xdma: Add terminate_all/synchroniz= e callbacks") Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index c22701e76b69..0c7350863873 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -379,12 +379,9 @@ static int xdma_xfer_start(struct xdma_chan *xchan) */ static int xdma_xfer_stop(struct xdma_chan *xchan) { - struct virt_dma_desc *vd =3D vchan_next_desc(&xchan->vchan); - struct xdma_device *xdev =3D xchan->xdev_hdl; int ret; - - if (!vd || !xchan->busy) - return -EINVAL; + u32 val; + struct xdma_device *xdev =3D xchan->xdev_hdl; =20 /* clear run stop bit to prevent any further auto-triggering */ ret =3D regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_CONTROL_W1C, @@ -392,7 +389,10 @@ static int xdma_xfer_stop(struct xdma_chan *xchan) if (ret) return ret; =20 - xchan->busy =3D false; + /* Clear the channel status register */ + ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS_RC, &val); + if (ret) + return ret; =20 return 0; } @@ -505,25 +505,25 @@ static void xdma_issue_pending(struct dma_chan *chan) static int xdma_terminate_all(struct dma_chan *chan) { struct xdma_chan *xdma_chan =3D to_xdma_chan(chan); - struct xdma_desc *desc =3D NULL; struct virt_dma_desc *vd; unsigned long flags; LIST_HEAD(head); =20 - spin_lock_irqsave(&xdma_chan->vchan.lock, flags); xdma_xfer_stop(xdma_chan); =20 + spin_lock_irqsave(&xdma_chan->vchan.lock, flags); + + xdma_chan->busy =3D false; vd =3D vchan_next_desc(&xdma_chan->vchan); - if (vd) - desc =3D to_xdma_desc(vd); - if (desc) { - dma_cookie_complete(&desc->vdesc.tx); - vchan_terminate_vdesc(&desc->vdesc); + if (vd) { + list_del(&vd->node); + dma_cookie_complete(&vd->tx); + vchan_terminate_vdesc(vd); } - vchan_get_all_descriptors(&xdma_chan->vchan, &head); + list_splice_tail(&head, &xdma_chan->vchan.desc_terminated); + spin_unlock_irqrestore(&xdma_chan->vchan.lock, flags); - vchan_dma_desc_free_list(&xdma_chan->vchan, &head); =20 return 0; } --=20 2.34.1 From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E852C3D0DD; Mon, 18 Dec 2023 11:40:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="KwrBueKy" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 0C0D42D0186C; Mon, 18 Dec 2023 12:40:28 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id Va4eSrGRR6VO; Mon, 18 Dec 2023 12:40:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id B4E872D0186B; Mon, 18 Dec 2023 12:40:27 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl B4E872D0186B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899627; bh=hzel1/ce/1mP1V20RRQos9BIDs2j5BOkjFb4gEFtAeQ=; h=From:To:Date:Message-Id:MIME-Version; b=KwrBueKy4tMDlYb+GHVFyiKUQXe89KVYvhYuoZmEACjYWolaFkshVXU9EgdByEY1X SvQyZ5+I8OlXdFMTd1k6QJ+5edd+KnDavDF0iQ72wN/5TA5jRHRwFpjwKpbQ6+YXMC +Y22ixURvIrN/XRn2WAB/KxGGdc3uAYQGQ6kUKirW0gkMhkAUs7ZOKEty1V1K/Tx9/ m7uqOHtZvQBMvuUJs+1EDyXU+u3sQFO47sET0RU6LLaEOmOdYJUnmYSV6BDd4vQk5k WOpYDaMT8UuK4AODlOubZWCdN9mSQtUudqCLql8YX3aCQvnlgt68hSurmJBsZBQWP2 sbN0wSu+r05VQ== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id hiZwfRKIXf4w; Mon, 18 Dec 2023 12:40:27 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 7FF5D2D01868; Mon, 18 Dec 2023 12:40:27 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 5/8] dmaengine: xilinx: xdma: Add error checking in xdma_channel_isr() Date: Mon, 18 Dec 2023 12:39:40 +0100 Message-Id: <20231218113943.9099-6-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check and clear the status register value before proceeding any further in xdma_channel_isr(). It is necessary to do it since the interrupt may occur on any error condition enabled at the start of a transfer. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 0c7350863873..9a1d2939a333 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -811,6 +811,18 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev= _id) desc =3D to_xdma_desc(vd); xdev =3D xchan->xdev_hdl; =20 + /* Clear-on-read the status register */ + ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS_RC, &st); + if (ret) + goto out; + + st &=3D XDMA_CHAN_STATUS_MASK; + if ((st & XDMA_CHAN_ERROR_MASK) || + !(st & (CHAN_CTRL_IE_DESC_COMPLETED | CHAN_CTRL_IE_DESC_STOPPED))) { + xdma_err(xdev, "channel error, status register value: 0x%x", st); + goto out; + } + ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_COMPLETED_DESC, &complete_desc_num); if (ret) @@ -818,14 +830,6 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev= _id) =20 if (desc->cyclic) { desc->completed_desc_num =3D complete_desc_num; - - ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, - &st); - if (ret) - goto out; - - regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, st); - vchan_cyclic_callback(vd); } else { xchan->busy =3D false; --=20 2.34.1 From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 842CE4184B; Mon, 18 Dec 2023 11:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="qu3DoTzS" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 5D1692D0186E; Mon, 18 Dec 2023 12:40:36 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id tu6U9_FKSmPL; Mon, 18 Dec 2023 12:40:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 0F8972D0186C; Mon, 18 Dec 2023 12:40:36 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl 0F8972D0186C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899636; bh=IeY0xEqvRU/tflVyxzoSpRy4NcybNFbv4E5J5gvXP2c=; h=From:To:Date:Message-Id:MIME-Version; b=qu3DoTzSt12x3+ZlG1PDBTF0MtgreNiFQrhpnM5nHNh3qp09HJzA1DXhp7v1RGGe7 miabCs6OjDIdcDdcWgPUL/NkvfCnClZBLo6CsQF7Dd+9ire7yYiZjRRzkjR9dAgphX +JyWDK+ttjIsq5952dsotzOvk393G8sGrStfYWk89vGSz+/hIjri9x3IXR4iBAEhtk GBWUHF2F1tSbN5T37eY6UXSW1mH53kb8XpcHayr531c1AIK+qHEHtxdUDCTX+xpl2p RTQHGKI8NAI+oyJg3Z/A+bzU8/t/YDw9ytW/1h/9P8A3g98xvuVFMioftkaFmdyqGa GeVzUcBIpFGQw== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id Zlyx9Lf6UWop; Mon, 18 Dec 2023 12:40:36 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id CC2DA2D01868; Mon, 18 Dec 2023 12:40:35 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 6/8] dmaengine: xilinx: xdma: Add transfer error reporting Date: Mon, 18 Dec 2023 12:39:41 +0100 Message-Id: <20231218113943.9099-7-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the capability of transfer status reporting. Introduce error flag, which allows to report error in case of a interrupt-reported error condition. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 9a1d2939a333..9f8597ed9be2 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -85,6 +85,7 @@ struct xdma_chan { * @cyclic: Cyclic transfer vs. scatter-gather * @periods: Number of periods in the cyclic transfer * @period_size: Size of a period in bytes in cyclic transfers + * @error: tx error flag */ struct xdma_desc { struct virt_dma_desc vdesc; @@ -97,6 +98,7 @@ struct xdma_desc { bool cyclic; u32 periods; u32 period_size; + bool error; }; =20 #define XDMA_DEV_STATUS_REG_DMA BIT(0) @@ -274,6 +276,7 @@ xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num, b= ool cyclic) sw_desc->chan =3D chan; sw_desc->desc_num =3D desc_num; sw_desc->cyclic =3D cyclic; + sw_desc->error =3D false; dblk_num =3D DIV_ROUND_UP(desc_num, XDMA_DESC_ADJACENT); sw_desc->desc_blocks =3D kcalloc(dblk_num, sizeof(*sw_desc->desc_blocks), GFP_NOWAIT); @@ -769,20 +772,20 @@ static enum dma_status xdma_tx_status(struct dma_chan= *chan, dma_cookie_t cookie spin_lock_irqsave(&xdma_chan->vchan.lock, flags); =20 vd =3D vchan_find_desc(&xdma_chan->vchan, cookie); - if (vd) - desc =3D to_xdma_desc(vd); - if (!desc || !desc->cyclic) { - spin_unlock_irqrestore(&xdma_chan->vchan.lock, flags); - return ret; - } - - period_idx =3D desc->completed_desc_num % desc->periods; - residue =3D (desc->periods - period_idx) * desc->period_size; + if (!vd) + goto out; =20 + desc =3D to_xdma_desc(vd); + if (desc->error) { + ret =3D DMA_ERROR; + } else if (desc->cyclic) { + period_idx =3D desc->completed_desc_num % desc->periods; + residue =3D (desc->periods - period_idx) * desc->period_size; + dma_set_residue(state, residue); + } +out: spin_unlock_irqrestore(&xdma_chan->vchan.lock, flags); =20 - dma_set_residue(state, residue); - return ret; } =20 @@ -819,6 +822,7 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_= id) st &=3D XDMA_CHAN_STATUS_MASK; if ((st & XDMA_CHAN_ERROR_MASK) || !(st & (CHAN_CTRL_IE_DESC_COMPLETED | CHAN_CTRL_IE_DESC_STOPPED))) { + desc->error =3D true; xdma_err(xdev, "channel error, status register value: 0x%x", st); goto out; } --=20 2.34.1 From nobody Tue Dec 16 12:22:41 2025 Received: from helios.alatek.com.pl (helios.alatek.com.pl [85.14.123.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B620E45BFD; Mon, 18 Dec 2023 11:40:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alatek.krakow.pl Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=alatek.krakow.pl header.i=@alatek.krakow.pl header.b="Mt9FtNaR" Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 95BB32D01870; Mon, 18 Dec 2023 12:40:43 +0100 (CET) Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10032) with ESMTP id ObOH1dHixr_c; Mon, 18 Dec 2023 12:40:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by helios.alatek.com.pl (Postfix) with ESMTP id 327B72D0186E; Mon, 18 Dec 2023 12:40:43 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 helios.alatek.com.pl 327B72D0186E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alatek.krakow.pl; s=99EE5E86-D06A-11EC-BE24-DBCCD0A148D3; t=1702899643; bh=iRrOYs5fy78KBnzCcFa+LVG7TpXXk3UuSZKby9LxYVk=; h=From:To:Date:Message-Id:MIME-Version; b=Mt9FtNaRGBmjVxcHb6hn2LcD07W2iTesGSFwJX0gxnp8IOBxZDXXSBbZaBhUbVN1Q vO2f1I1uCfcC2jrr+jwYwJ/8AH6nxqIZ3y+V6LZonZK7c5gStuiSwyrvjW8Dwl/fNt G/33n9tqry3oMAF1BTMf+rtgN8wZSZeSumiXlQQkD1ztjmwzkharRCgs8aWEl2DlJE vHdpTQEZfAOqeELWmzE4bPtNho8fqI4fdY5+ZqYchmRP9mmtiQ/eXahJLPOes3TYNz jQUvAqmncm2Nxvl3PVmbPea/pXg3x4sr83R/wZvppxnGAR/sMnHvw1CVUodmDU3eAh tJIkqqtdNYGUA== X-Virus-Scanned: amavis at alatek.com.pl Received: from helios.alatek.com.pl ([127.0.0.1]) by localhost (helios.alatek.com.pl [127.0.0.1]) (amavis, port 10026) with ESMTP id siF46F4BckZb; Mon, 18 Dec 2023 12:40:43 +0100 (CET) Received: from ideapad.. (unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 033732D01868; Mon, 18 Dec 2023 12:40:43 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 7/8] dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA transfers Date: Mon, 18 Dec 2023 12:39:42 +0100 Message-Id: <20231218113943.9099-8-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make generic code generic. As descriptor-filling logic stays the same regardless of a dmaengine's type of transfer, it is possible to write the descriptor-filling function in a generic way, so that it can be used for every single type of transfer preparation callback. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma.c | 101 +++++++++++++++++++++----------------- 1 file changed, 57 insertions(+), 44 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 9f8597ed9be2..618cc9af6eb9 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -542,6 +542,43 @@ static void xdma_synchronize(struct dma_chan *chan) vchan_synchronize(&xdma_chan->vchan); } =20 +/** + * xdma_fill_descs - Fill hardware descriptors with contiguous memory bloc= k addresses + * @sw_desc - tx descriptor state container + * @src_addr - Value for a ->src_addr field of a first descriptor + * @dst_addr - Value for a ->dst_addr field of a first descriptor + * @size - Total size of a contiguous memory block + * @filled_descs_num - Number of filled hardware descriptors for correspon= ding sw_desc + */ +static inline u32 xdma_fill_descs(struct xdma_desc *sw_desc, u64 src_addr, + u64 dst_addr, u32 size, u32 filled_descs_num) +{ + u32 left =3D size, len, desc_num =3D filled_descs_num; + struct xdma_desc_block *dblk; + struct xdma_hw_desc *desc; + + dblk =3D sw_desc->desc_blocks + (desc_num / XDMA_DESC_ADJACENT); + desc =3D dblk->virt_addr; + desc +=3D desc_num & XDMA_DESC_ADJACENT_MASK; + do { + len =3D min_t(u32, left, XDMA_DESC_BLEN_MAX); + /* set hardware descriptor */ + desc->bytes =3D cpu_to_le32(len); + desc->src_addr =3D cpu_to_le64(src_addr); + desc->dst_addr =3D cpu_to_le64(dst_addr); + if (!(++desc_num & XDMA_DESC_ADJACENT_MASK)) + desc =3D (++dblk)->virt_addr; + else + desc++; + + src_addr +=3D len; + dst_addr +=3D len; + left -=3D len; + } while (left); + + return desc_num - filled_descs_num; +} + /** * xdma_prep_device_sg - prepare a descriptor for a DMA transaction * @chan: DMA channel pointer @@ -558,13 +595,10 @@ xdma_prep_device_sg(struct dma_chan *chan, struct sca= tterlist *sgl, { struct xdma_chan *xdma_chan =3D to_xdma_chan(chan); struct dma_async_tx_descriptor *tx_desc; - u32 desc_num =3D 0, i, len, rest; - struct xdma_desc_block *dblk; - struct xdma_hw_desc *desc; struct xdma_desc *sw_desc; - u64 dev_addr, *src, *dst; + u32 desc_num =3D 0, i; + u64 addr, dev_addr, *src, *dst; struct scatterlist *sg; - u64 addr; =20 for_each_sg(sgl, sg, sg_len, i) desc_num +=3D DIV_ROUND_UP(sg_dma_len(sg), XDMA_DESC_BLEN_MAX); @@ -584,32 +618,11 @@ xdma_prep_device_sg(struct dma_chan *chan, struct sca= tterlist *sgl, dst =3D &addr; } =20 - dblk =3D sw_desc->desc_blocks; - desc =3D dblk->virt_addr; - desc_num =3D 1; + desc_num =3D 0; for_each_sg(sgl, sg, sg_len, i) { addr =3D sg_dma_address(sg); - rest =3D sg_dma_len(sg); - - do { - len =3D min_t(u32, rest, XDMA_DESC_BLEN_MAX); - /* set hardware descriptor */ - desc->bytes =3D cpu_to_le32(len); - desc->src_addr =3D cpu_to_le64(*src); - desc->dst_addr =3D cpu_to_le64(*dst); - - if (!(desc_num & XDMA_DESC_ADJACENT_MASK)) { - dblk++; - desc =3D dblk->virt_addr; - } else { - desc++; - } - - desc_num++; - dev_addr +=3D len; - addr +=3D len; - rest -=3D len; - } while (rest); + desc_num +=3D xdma_fill_descs(sw_desc, *src, *dst, sg_dma_len(sg), desc_= num); + dev_addr +=3D sg_dma_len(sg); } =20 tx_desc =3D vchan_tx_prep(&xdma_chan->vchan, &sw_desc->vdesc, flags); @@ -643,9 +656,9 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t = address, struct xdma_device *xdev =3D xdma_chan->xdev_hdl; unsigned int periods =3D size / period_size; struct dma_async_tx_descriptor *tx_desc; - struct xdma_desc_block *dblk; - struct xdma_hw_desc *desc; struct xdma_desc *sw_desc; + u64 addr, dev_addr, *src, *dst; + u32 desc_num; unsigned int i; =20 /* @@ -670,21 +683,21 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_= t address, sw_desc->period_size =3D period_size; sw_desc->dir =3D dir; =20 - dblk =3D sw_desc->desc_blocks; - desc =3D dblk->virt_addr; + addr =3D address; + if (dir =3D=3D DMA_MEM_TO_DEV) { + dev_addr =3D xdma_chan->cfg.dst_addr; + src =3D &addr; + dst =3D &dev_addr; + } else { + dev_addr =3D xdma_chan->cfg.src_addr; + src =3D &dev_addr; + dst =3D &addr; + } =20 - /* fill hardware descriptor */ + desc_num =3D 0; for (i =3D 0; i < periods; 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(unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 8D8E32D01868; Mon, 18 Dec 2023 12:40:52 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Cc: jankul@alatek.krakow.pl Subject: [PATCH v5 8/8] dmaengine: xilinx: xdma: Implement interleaved DMA transfers Date: Mon, 18 Dec 2023 12:39:43 +0100 Message-Id: <20231218113943.9099-9-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113904.9071-1-jankul@alatek.krakow.pl> References: <20231218113904.9071-1-jankul@alatek.krakow.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Interleaved DMA functionality allows dmaengine clients' to express DMA transfers in an arbitrary way. This is extremely useful in FPGA environments, where a greater transfer flexibility is needed. For instance, in one FPGA design there may be need to do DMA to/from a FIFO at a fixed address, and also to do DMA to/from a (non)contiguous RAM memory. Introduce separate tx preparation callback and add tx-flags handling logic. Their behavior is based on the description of interleaved DMA transfers in both source code and the DMAEngine's documentation. Since XDMA is a fully-fledged scatter-gather dma engine, the logic of xdma_prep_interleaved_dma() is fairly simple and similar to the other tx preparation callbacks. The whole tx-flags handling logic resides in xdma_channel_isr(). Transfer of a single frame from a interleaved DMA transfer template is pretty similar to the single sg transaction. Therefore, the transaction of the whole interleaved DMA transfer template is basically a cyclic dma transaction with finite cycles/periods (equal to the frame of count) of a single sg transfers. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma.c | 107 ++++++++++++++++++++++++++++++++++---- 1 file changed, 98 insertions(+), 9 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 618cc9af6eb9..9360b85131ef 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -83,8 +83,10 @@ struct xdma_chan { * @desc_num: Number of hardware descriptors * @completed_desc_num: Completed hardware descriptors * @cyclic: Cyclic transfer vs. scatter-gather + * @interleaved_dma: Interleaved DMA transfer * @periods: Number of periods in the cyclic transfer * @period_size: Size of a period in bytes in cyclic transfers + * @frames_left: Number of frames left in interleaved DMA transfer * @error: tx error flag */ struct xdma_desc { @@ -96,8 +98,10 @@ struct xdma_desc { u32 desc_num; u32 completed_desc_num; bool cyclic; + bool interleaved_dma; u32 periods; u32 period_size; + u32 frames_left; bool error; }; =20 @@ -607,6 +611,8 @@ xdma_prep_device_sg(struct dma_chan *chan, struct scatt= erlist *sgl, if (!sw_desc) return NULL; sw_desc->dir =3D dir; + sw_desc->cyclic =3D false; + sw_desc->interleaved_dma =3D false; =20 if (dir =3D=3D DMA_MEM_TO_DEV) { dev_addr =3D xdma_chan->cfg.dst_addr; @@ -682,6 +688,7 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t = address, sw_desc->periods =3D periods; sw_desc->period_size =3D period_size; sw_desc->dir =3D dir; + sw_desc->interleaved_dma =3D false; =20 addr =3D address; if (dir =3D=3D DMA_MEM_TO_DEV) { @@ -712,6 +719,57 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t= address, return NULL; } =20 +/** + * xdma_prep_interleaved_dma - Prepare virtual descriptor for interleaved = DMA transfers + * @chan: DMA channel + * @xt: DMA transfer template + * @flags: tx flags + */ +struct dma_async_tx_descriptor * +xdma_prep_interleaved_dma(struct dma_chan *chan, + struct dma_interleaved_template *xt, + unsigned long flags) +{ + int i; + u32 desc_num =3D 0, period_size =3D 0; + struct dma_async_tx_descriptor *tx_desc; + struct xdma_chan *xchan =3D to_xdma_chan(chan); + struct xdma_desc *sw_desc; + u64 src_addr, dst_addr; + + for (i =3D 0; i < xt->frame_size; ++i) + desc_num +=3D DIV_ROUND_UP(xt->sgl[i].size, XDMA_DESC_BLEN_MAX); + + sw_desc =3D xdma_alloc_desc(xchan, desc_num, false); + if (!sw_desc) + return NULL; + sw_desc->dir =3D xt->dir; + sw_desc->interleaved_dma =3D true; + sw_desc->cyclic =3D flags & DMA_PREP_REPEAT; + sw_desc->frames_left =3D xt->numf; + sw_desc->periods =3D xt->numf; + + desc_num =3D 0; + src_addr =3D xt->src_start; + dst_addr =3D xt->dst_start; + for (i =3D 0; i < xt->frame_size; ++i) { + desc_num +=3D xdma_fill_descs(sw_desc, src_addr, dst_addr, xt->sgl[i].si= ze, desc_num); + src_addr +=3D dmaengine_get_src_icg(xt, &xt->sgl[i]) + xt->src_inc ? + xt->sgl[i].size : 0; + dst_addr +=3D dmaengine_get_dst_icg(xt, &xt->sgl[i]) + xt->dst_inc ? + xt->sgl[i].size : 0; + period_size +=3D xt->sgl[i].size; + } + sw_desc->period_size =3D period_size; + + tx_desc =3D vchan_tx_prep(&xchan->vchan, &sw_desc->vdesc, flags); + if (tx_desc) + return tx_desc; + + xdma_free_desc(&sw_desc->vdesc); + return NULL; +} + /** * xdma_device_config - Configure the DMA channel * @chan: DMA channel @@ -811,11 +869,12 @@ static irqreturn_t xdma_channel_isr(int irq, void *de= v_id) { struct xdma_chan *xchan =3D dev_id; u32 complete_desc_num =3D 0; - struct xdma_device *xdev; - struct virt_dma_desc *vd; + struct xdma_device *xdev =3D xchan->xdev_hdl; + struct virt_dma_desc *vd, *next_vd; struct xdma_desc *desc; int ret; u32 st; + bool repeat_tx; =20 spin_lock(&xchan->vchan.lock); =20 @@ -824,9 +883,6 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_= id) if (!vd) goto out; =20 - desc =3D to_xdma_desc(vd); - xdev =3D xchan->xdev_hdl; - /* Clear-on-read the status register */ ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS_RC, &st); if (ret) @@ -845,10 +901,36 @@ static irqreturn_t xdma_channel_isr(int irq, void *de= v_id) if (ret) goto out; =20 - if (desc->cyclic) { - desc->completed_desc_num =3D complete_desc_num; - vchan_cyclic_callback(vd); - } else { + desc =3D to_xdma_desc(vd); + if (desc->interleaved_dma) { + xchan->busy =3D false; + desc->completed_desc_num +=3D complete_desc_num; + if (complete_desc_num =3D=3D XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT) { + xdma_xfer_start(xchan); + goto out; + } + + /* last desc of any frame */ + desc->frames_left--; + if (desc->frames_left) + goto out; + + /* last desc of the last frame */ + repeat_tx =3D vd->tx.flags & DMA_PREP_REPEAT; + next_vd =3D list_first_entry_or_null(&vd->node, struct virt_dma_desc, no= de); + if (next_vd) + repeat_tx =3D repeat_tx && !(next_vd->tx.flags & DMA_PREP_LOAD_EOT); + if (repeat_tx) { + desc->frames_left =3D desc->periods; + desc->completed_desc_num =3D 0; + vchan_cyclic_callback(vd); + } else { + list_del(&vd->node); + vchan_cookie_complete(vd); + } + /* start (or continue) the tx of a first desc on the vc.desc_issued list= , if any */ + xdma_xfer_start(xchan); + } else if (!desc->cyclic) { xchan->busy =3D false; desc->completed_desc_num +=3D complete_desc_num; =20 @@ -865,6 +947,9 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_= id) =20 /* transfer the rest of data */ xdma_xfer_start(xchan); + } else { + desc->completed_desc_num =3D complete_desc_num; + vchan_cyclic_callback(vd); } =20 out: @@ -1163,6 +1248,9 @@ static int xdma_probe(struct platform_device *pdev) dma_cap_set(DMA_SLAVE, xdev->dma_dev.cap_mask); dma_cap_set(DMA_PRIVATE, xdev->dma_dev.cap_mask); dma_cap_set(DMA_CYCLIC, xdev->dma_dev.cap_mask); + dma_cap_set(DMA_INTERLEAVE, xdev->dma_dev.cap_mask); + dma_cap_set(DMA_REPEAT, xdev->dma_dev.cap_mask); + dma_cap_set(DMA_LOAD_EOT, xdev->dma_dev.cap_mask); =20 xdev->dma_dev.dev =3D &pdev->dev; xdev->dma_dev.residue_granularity =3D DMA_RESIDUE_GRANULARITY_SEGMENT; @@ -1178,6 +1266,7 @@ static int xdma_probe(struct platform_device *pdev) xdev->dma_dev.filter.mapcnt =3D pdata->device_map_cnt; xdev->dma_dev.filter.fn =3D xdma_filter_fn; xdev->dma_dev.device_prep_dma_cyclic =3D xdma_prep_dma_cyclic; + xdev->dma_dev.device_prep_interleaved_dma =3D xdma_prep_interleaved_dma; =20 ret =3D dma_async_device_register(&xdev->dma_dev); if (ret) { --=20 2.34.1