From nobody Sat Dec 27 18:55:43 2025 Received: from mail-ot1-f45.google.com (mail-ot1-f45.google.com [209.85.210.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4322115E98 for ; Mon, 18 Dec 2023 10:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="WtH5fJIX" Received: by mail-ot1-f45.google.com with SMTP id 46e09a7af769-6d9d29a2332so1256712a34.0 for ; Mon, 18 Dec 2023 02:41:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1702896078; x=1703500878; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EzYVT3U62jOpimrVBwbFtsr3YzUGPIXyIVj0onyqTs4=; b=WtH5fJIX6zigazMmQLZNqE4vdxwNUnwY5Lta2nOIAxsy0eQL4KNqxlkE8zo2zfmW1N hUoh0rvtG2fyB6TlyHZNmoR/kMv2+DYuNcZazV/2SGiRUsn255ppkcYxjEnMgF23Sh57 3oYc22swfDMVjK5/RJ0Oeqn4BdofM1GwQghpJ5hsteEHaRb+vjDvJ/NBFT+UeQ47Qy23 ua2cIuxASJO3kYfVMzBEu9mf/eI9stLDfOPYkYCHvHG+pdu3iVj2NHRQmmm8FYaUEy/K CkiOGNLM+fBH5xmZDddnX+lapJLmAL569zpZyK6Up1FwMrWgbTaXsPxI/tICooBkLVFP EluQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702896078; x=1703500878; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EzYVT3U62jOpimrVBwbFtsr3YzUGPIXyIVj0onyqTs4=; b=cbbQiKtQTjTq0bAK+Y1hYHqbmFBb6GSHROU71mwazpozP6GJseFEuudBt0x1RrHmcG KFTIpSJ9XRFoBPJVJLhELFtQCoNBrSMCN7epkmHtxvRgn2/c2PiLazE2rxJig3qnQWzk tW2c4hCj7ybqh5A1XXoIslpafcoutMNaX4YC7etyWSkfJdW26E7BBqjcCkmt+20MXoNr QhU/4ZQ5RWz7CTRb8C5fP89VhgJNBwV2nVx/8AzxGUXBnLSi3lxlu8r74HxbG4k9dehH jXOWjY6Z2sG6eoav2YIEY3wrZDqvmklamJveE/HnQoZUN21y0JGNzTEvqk9Dd2lMg62Y 3K8A== X-Gm-Message-State: AOJu0YydvOllivHmsJmVj1BDS6/Avfzk5yGHJI3i1m/hcpMpmBKJYTFk j0HbssdLWvgRAk/kbzBWWhbX0xpXBYgV2oBZnhQ= X-Google-Smtp-Source: AGHT+IHap3UnechuN3domT4X1LYxQydZehOxW5SUbyRuhBv7FJIHHp0fJMugr+7DMK4DyTgTcIzVvg== X-Received: by 2002:a9d:7dc9:0:b0:6da:5056:62de with SMTP id k9-20020a9d7dc9000000b006da505662demr2117996otn.7.1702896078450; Mon, 18 Dec 2023 02:41:18 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 185-20020a4a1ac2000000b005907ad9f302sm574970oof.37.2023.12.18.02.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 02:41:18 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Conor Dooley , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v1 01/10] RISC-V: Fix the typo in Scountovf CSR name Date: Mon, 18 Dec 2023 02:40:58 -0800 Message-Id: <20231218104107.2976925-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218104107.2976925-1-atishp@rivosinc.com> References: <20231218104107.2976925-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 2 +- arch/riscv/include/asm/errata_list.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 306a19a5509c..88cdc8a3e654 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f =20 -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 =20 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 83ed25e43553..7026fba12eeb 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -152,7 +152,7 @@ asm volatile(ALTERNATIVE_2( \ =20 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU) \ --=20 2.34.1