From nobody Thu Dec 18 16:18:12 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E595B13AC9 for ; Mon, 18 Dec 2023 10:03:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BIA3Mj0071114; Mon, 18 Dec 2023 18:03:22 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4StwGb0q0Jz2Pj8FH; Mon, 18 Dec 2023 17:57:11 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Mon, 18 Dec 2023 18:03:20 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , LKML , Chunyan Zhang Subject: [PATCH V2 1/3] dt-bindings: mfd: sprd: Add support for UMS9620 Date: Mon, 18 Dec 2023 18:02:32 +0800 Message-ID: <20231218100234.1102916-2-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231218100234.1102916-1-chunyan.zhang@unisoc.com> References: <20231218100234.1102916-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BIA3Mj0071114 Content-Type: text/plain; charset="utf-8" Add bindings for Unisoc UMS9620 system global registers which provide register maps for clocks. Signed-off-by: Chunyan Zhang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml = b/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml index 996bd4a17ca3..a750fa23d7e7 100644 --- a/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml +++ b/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml @@ -19,7 +19,9 @@ description: properties: compatible: items: - - const: sprd,ums512-glbregs + - enum: + - sprd,ums512-glbregs + - sprd,ums9620-glbregs - const: syscon - const: simple-mfd =20 --=20 2.41.0 From nobody Thu Dec 18 16:18:12 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E58BD13AC3 for ; Mon, 18 Dec 2023 10:03:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BIA3N49071157; Mon, 18 Dec 2023 18:03:23 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4StwGc1scHz2Pj8Dm; Mon, 18 Dec 2023 17:57:12 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Mon, 18 Dec 2023 18:03:21 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , LKML , Chunyan Zhang Subject: [PATCH V2 2/3] dt-bindings: arm: Add compatible strings for Unisoc's UMS9620 Date: Mon, 18 Dec 2023 18:02:33 +0800 Message-ID: <20231218100234.1102916-3-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231218100234.1102916-1-chunyan.zhang@unisoc.com> References: <20231218100234.1102916-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BIA3N49071157 Content-Type: text/plain; charset="utf-8" Added bindings for Unisoc's UMS9620-2H10 board and UMS9620 SoC. Signed-off-by: Chunyan Zhang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/sprd/sprd.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml b/Documen= tation/devicetree/bindings/arm/sprd/sprd.yaml index eaa67b8e0d6c..40fc3c8b9dce 100644 --- a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml +++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml @@ -35,6 +35,11 @@ properties: - sprd,ums512-1h10 - const: sprd,ums512 =20 + - items: + - enum: + - sprd,ums9620-2h10 + - const: sprd,ums9620 + additionalProperties: true =20 ... --=20 2.41.0 From nobody Thu Dec 18 16:18:12 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 929D714F77 for ; Mon, 18 Dec 2023 10:03:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BIA3Opp071197; Mon, 18 Dec 2023 18:03:24 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4StwGd3Fqmz2Pj8FL; Mon, 18 Dec 2023 17:57:13 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Mon, 18 Dec 2023 18:03:22 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , LKML , Chunyan Zhang Subject: [PATCH V2 3/3] arm64: dts: sprd: Add support for Unisoc's UMS9620 Date: Mon, 18 Dec 2023 18:02:34 +0800 Message-ID: <20231218100234.1102916-4-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231218100234.1102916-1-chunyan.zhang@unisoc.com> References: <20231218100234.1102916-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BIA3Opp071197 Content-Type: text/plain; charset="utf-8" Add basic support for Unisoc's UMS9620, with this patch, the board ums9620-2h10 can run into console. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/Makefile | 3 +- arch/arm64/boot/dts/sprd/ums9620-2h10.dts | 38 ++++ arch/arm64/boot/dts/sprd/ums9620.dtsi | 245 ++++++++++++++++++++++ 3 files changed, 285 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/sprd/ums9620-2h10.dts create mode 100644 arch/arm64/boot/dts/sprd/ums9620.dtsi diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/M= akefile index 97522fb0bf66..3ce81ad7116f 100644 --- a/arch/arm64/boot/dts/sprd/Makefile +++ b/arch/arm64/boot/dts/sprd/Makefile @@ -2,4 +2,5 @@ dtb-$(CONFIG_ARCH_SPRD) +=3D sc9836-openphone.dtb \ sp9860g-1h10.dtb \ sp9863a-1h10.dtb \ - ums512-1h10.dtb + ums512-1h10.dtb \ + ums9620-2h10.dtb diff --git a/arch/arm64/boot/dts/sprd/ums9620-2h10.dts b/arch/arm64/boot/dt= s/sprd/ums9620-2h10.dts new file mode 100644 index 000000000000..b35671192a72 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums9620-2h10.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS9620-2h10 board DTS file + * + * Copyright (C) 2023, Unisoc Inc. + */ + +/dts-v1/; + +#include "ums9620.dtsi" + +/ { + model =3D "Unisoc UMS9620-2H10 Board"; + + compatible =3D "sprd,ums9620-2h10", "sprd,ums9620"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + chosen { + stdout-path =3D "serial1:921600n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/sprd/ums9620.dtsi b/arch/arm64/boot/dts/sp= rd/ums9620.dtsi new file mode 100644 index 000000000000..2191f0a4811b --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums9620.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS9620 DTS file + * + * Copyright (C) 2023, Unisoc Inc. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + core1 { + cpu =3D <&CPU1>; + }; + core2 { + cpu =3D <&CPU2>; + }; + core3 { + cpu =3D <&CPU3>; + }; + core4 { + cpu =3D <&CPU4>; + }; + core5 { + cpu =3D <&CPU5>; + }; + core6 { + cpu =3D <&CPU6>; + }; + core7 { + cpu =3D <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + cpu-idle-states =3D <&LIT_CORE_PD>; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + cpu-idle-states =3D <&LIT_CORE_PD>; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + cpu-idle-states =3D <&LIT_CORE_PD>; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + cpu-idle-states =3D <&LIT_CORE_PD>; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + cpu-idle-states =3D <&BIG_CORE_PD>; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + cpu-idle-states =3D <&BIG_CORE_PD>; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + cpu-idle-states =3D <&BIG_CORE_PD>; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + cpu-idle-states =3D <&BIG_CORE_PD>; + }; + }; + + idle-states { + entry-method =3D "psci"; + LIT_CORE_PD: cpu-pd-lit { + compatible =3D "arm,idle-state"; + entry-latency-us =3D <1000>; + exit-latency-us =3D <500>; + min-residency-us =3D <2500>; + local-timer-stop; + arm,psci-suspend-param =3D <0x00010000>; + }; + + BIG_CORE_PD: cpu-pd-big { + compatible =3D "arm,idle-state"; + entry-latency-us =3D <4000>; + exit-latency-us =3D <4000>; + min-residency-us =3D <10000>; + local-timer-stop; + arm,psci-suspend-param =3D <0x00010000>; + }; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* Physical Secure PPI = */ + , /* Physical Non-Secure PPI */ + , /* Virtual PPI */ + ; /* Hipervisor PPI */ + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D , + , + , + , + , + , + , + ; + }; + + soc: soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@12000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x12000000 0 0x20000>, /* GICD */ + <0x0 0x12040000 0 0x100000>; /* GICR */ + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + redistributor-stride =3D <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions =3D <1>; + interrupt-controller; + interrupts =3D ; + }; + + apb@20200000 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0x20200000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + uart0: serial@0 { + compatible =3D "sprd,ums9620-uart", + "sprd,sc9836-uart"; + reg =3D <0 0x100>; + interrupts =3D ; + clocks =3D <&ext_26m>; + status =3D "disabled"; + }; + + uart1: serial@10000 { + compatible =3D "sprd,ums9620-uart", + "sprd,sc9836-uart"; + reg =3D <0x10000 0x100>; + interrupts =3D ; + clocks =3D <&ext_26m>; + status =3D "disabled"; + }; + }; + }; + + ext_26m: clk-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "ext-26m"; + }; + + ext_4m: clk-4m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <4000000>; + clock-output-names =3D "ext-4m"; + }; + + ext_32k: clk-32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "ext-32k"; + }; + + rco_100m: clk-100m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + clock-output-names =3D "rco-100m"; + }; + + dphy_312m5: dphy-312m5 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <312500000>; + clock-output-names =3D "dphy-312m5"; + }; + + dphy_416m7: dphy-416m7 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <416700000>; + clock-output-names =3D "dphy-416m7"; + }; +}; --=20 2.41.0