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charset="utf-8" Refactors the clock handling logic in the imx6 PCI driver by adding clk_names[] define in drvdata . Simplifies the code and makes it more maintainable, as future additions of SOC support will only require straightforward changes. Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - using clk_bulk_*() API Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 128 ++++++++------------------ 1 file changed, 38 insertions(+), 90 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 74703362aeec7..2086214345e9a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,12 +61,15 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) =20 +#define IMX6_PCIE_MAX_CLKS 6 + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; u32 flags; int dbi_length; const char *gpr; + const char *clk_names[IMX6_PCIE_MAX_CLKS]; }; =20 struct imx6_pcie { @@ -74,11 +77,8 @@ struct imx6_pcie { int reset_gpio; bool gpio_active_high; bool link_is_up; - struct clk *pcie_bus; - struct clk *pcie_phy; - struct clk *pcie_inbound_axi; - struct clk *pcie; - struct clk *pcie_aux; + struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; + u32 clks_cnt; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -407,13 +407,18 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct i= mx6_pcie *imx6_pcie) =20 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) { - unsigned long phy_rate =3D clk_get_rate(imx6_pcie->pcie_phy); + unsigned long phy_rate =3D 0; int mult, div; u16 val; + int i; =20 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) return 0; =20 + for (i =3D 0; i < imx6_pcie->clks_cnt; i++) + if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) =3D=3D 0) + phy_rate =3D clk_get_rate(imx6_pcie->clks[i].clk); + switch (phy_rate) { case 125000000: /* @@ -550,19 +555,11 @@ static int imx6_pcie_attach_pd(struct device *dev) =20 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) { - struct dw_pcie *pci =3D imx6_pcie->pci; - struct device *dev =3D pci->dev; unsigned int offset; int ret =3D 0; =20 switch (imx6_pcie->drvdata->variant) { case IMX6SX: - ret =3D clk_prepare_enable(imx6_pcie->pcie_inbound_axi); - if (ret) { - dev_err(dev, "unable to enable pcie_axi clock\n"); - break; - } - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; @@ -589,12 +586,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *= imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - ret =3D clk_prepare_enable(imx6_pcie->pcie_aux); - if (ret) { - dev_err(dev, "unable to enable pcie_aux clock\n"); - break; - } - offset =3D imx6_pcie_grp_offset(imx6_pcie); /* * Set the over ride low and enabled @@ -615,9 +606,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *i= mx6_pcie) static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) { switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); - break; case IMX6QP: case IMX6Q: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, @@ -631,14 +619,6 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie= *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - clk_disable_unprepare(imx6_pcie->pcie_aux); - break; default: break; } @@ -650,23 +630,9 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6= _pcie) struct device *dev =3D pci->dev; int ret; =20 - ret =3D clk_prepare_enable(imx6_pcie->pcie_phy); - if (ret) { - dev_err(dev, "unable to enable pcie_phy clock\n"); + ret =3D clk_bulk_prepare_enable(imx6_pcie->clks_cnt, imx6_pcie->clks); + if (ret) return ret; - } - - ret =3D clk_prepare_enable(imx6_pcie->pcie_bus); - if (ret) { - dev_err(dev, "unable to enable pcie_bus clock\n"); - goto err_pcie_bus; - } - - ret =3D clk_prepare_enable(imx6_pcie->pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clock\n"); - goto err_pcie; - } =20 ret =3D imx6_pcie_enable_ref_clk(imx6_pcie); if (ret) { @@ -679,11 +645,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6= _pcie) return 0; =20 err_ref_clk: - clk_disable_unprepare(imx6_pcie->pcie); -err_pcie: - clk_disable_unprepare(imx6_pcie->pcie_bus); -err_pcie_bus: - clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_bulk_disable_unprepare(imx6_pcie->clks_cnt, imx6_pcie->clks); =20 return ret; } @@ -691,9 +653,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_= pcie) static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) { imx6_pcie_disable_ref_clk(imx6_pcie); - clk_disable_unprepare(imx6_pcie->pcie); - clk_disable_unprepare(imx6_pcie->pcie_bus); - clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_bulk_disable_unprepare(imx6_pcie->clks_cnt, imx6_pcie->clks); } =20 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) @@ -1305,32 +1265,19 @@ static int imx6_pcie_probe(struct platform_device *= pdev) return imx6_pcie->reset_gpio; } =20 - /* Fetch clocks */ - imx6_pcie->pcie_bus =3D devm_clk_get(dev, "pcie_bus"); - if (IS_ERR(imx6_pcie->pcie_bus)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), - "pcie_bus clock source missing or invalid\n"); + while (imx6_pcie->drvdata->clk_names[imx6_pcie->clks_cnt]) { + int i =3D imx6_pcie->clks_cnt; =20 - imx6_pcie->pcie =3D devm_clk_get(dev, "pcie"); - if (IS_ERR(imx6_pcie->pcie)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), - "pcie clock source missing or invalid\n"); + imx6_pcie->clks[i].id =3D imx6_pcie->drvdata->clk_names[i]; + imx6_pcie->clks_cnt++; + } + + /* Fetch clocks */ + ret =3D devm_clk_bulk_get(dev, imx6_pcie->clks_cnt, imx6_pcie->clks); + if (ret) + return ret; =20 switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - imx6_pcie->pcie_inbound_axi =3D devm_clk_get(dev, - "pcie_inbound_axi"); - if (IS_ERR(imx6_pcie->pcie_inbound_axi)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), - "pcie_inbound_axi clock missing or invalid\n"); - break; - case IMX8MQ: - case IMX8MQ_EP: - imx6_pcie->pcie_aux =3D devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); - fallthrough; case IMX7D: if (dbi_base->start =3D=3D IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id =3D 1; @@ -1353,10 +1300,6 @@ static int imx6_pcie_probe(struct platform_device *p= dev) case IMX8MM_EP: case IMX8MP: case IMX8MP_EP: - imx6_pcie->pcie_aux =3D devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); imx6_pcie->apps_reset =3D devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) @@ -1372,14 +1315,6 @@ static int imx6_pcie_probe(struct platform_device *p= dev) default: break; } - /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */ - if (imx6_pcie->phy =3D=3D NULL) { - imx6_pcie->pcie_phy =3D devm_clk_get(dev, "pcie_phy"); - if (IS_ERR(imx6_pcie->pcie_phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), - "pcie_phy clock source missing or invalid\n"); - } - =20 /* Grab turnoff reset */ imx6_pcie->turnoff_reset =3D devm_reset_control_get_optional_exclusive(de= v, "turnoff"); @@ -1470,6 +1405,9 @@ static void imx6_pcie_shutdown(struct platform_device= *pdev) imx6_pcie_assert_core_reset(imx6_pcie); } =20 +#define IMX6_CLKS_COMMON "pcie_bus", "pcie" +#define IMX6_CLKS_NO_PHYDRV IMX6_CLKS_COMMON, "pcie_phy" + static const struct imx6_pcie_drvdata drvdata[] =3D { [IMX6Q] =3D { .variant =3D IMX6Q, @@ -1477,6 +1415,7 @@ static const struct imx6_pcie_drvdata drvdata[] =3D { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, .dbi_length =3D 0x200, .gpr =3D "fsl,imx6q-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_NO_PHYDRV}, }, [IMX6SX] =3D { .variant =3D IMX6SX, @@ -1484,6 +1423,7 @@ static const struct imx6_pcie_drvdata drvdata[] =3D { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx6q-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_NO_PHYDRV, "pcie_inbound_axi"}, }, [IMX6QP] =3D { .variant =3D IMX6QP, @@ -1492,40 +1432,48 @@ static const struct imx6_pcie_drvdata drvdata[] =3D= { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length =3D 0x200, .gpr =3D "fsl,imx6q-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_NO_PHYDRV}, }, [IMX7D] =3D { .variant =3D IMX7D, .flags =3D IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx7d-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_NO_PHYDRV}, }, [IMX8MQ] =3D { .variant =3D IMX8MQ, .gpr =3D "fsl,imx8mq-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, }, [IMX8MM] =3D { .variant =3D IMX8MM, .flags =3D IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx8mm-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP] =3D { .variant =3D IMX8MP, .flags =3D IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx8mp-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MQ_EP] =3D { .variant =3D IMX8MQ_EP, .mode =3D DW_PCIE_EP_TYPE, .gpr =3D "fsl,imx8mq-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_NO_PHYDRV, "pcie_aux"}, }, [IMX8MM_EP] =3D { .variant =3D IMX8MM_EP, .mode =3D DW_PCIE_EP_TYPE, .gpr =3D "fsl,imx8mm-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_COMMON, "pcie_aux"}, }, [IMX8MP_EP] =3D { .variant =3D IMX8MP_EP, .mode =3D DW_PCIE_EP_TYPE, .gpr =3D "fsl,imx8mp-iomuxc-gpr", + .clk_names =3D {IMX6_CLKS_COMMON, "pcie_aux"}, }, }; =20 --=20 2.34.1