From nobody Fri Sep 20 09:42:37 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 243EE18AF4 for ; Fri, 15 Dec 2023 08:51:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="dfCFG0/I" X-UUID: 14c63d1c9b2711eeba30773df0976c77-20231215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GQFrFJz8Fcv4o+QSkMTCins8sao8rmNVqzntXh3ULuY=; b=dfCFG0/ICqm3PqSD7IfUvYy9rC3IRQrGt/peC1oVUSKCOIGKv2SlbtbQx7qSO3cdVlQRg02dBH1vpfgN8X0jEivFBu1D2GJOg6kG/POwmFsRpypwR1vJsSkRdgHMz6TjYyE73GemhXrjttCFOB/V4+Fj/lw7t08vdPY7SmULfdU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:b58a52d1-b369-4589-8363-7aaa6eb9a4c5,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:a8e236bd-2ac7-4da2-9f94-677a477649d9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 14c63d1c9b2711eeba30773df0976c77-20231215 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 317183111; Fri, 15 Dec 2023 16:51:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 15 Dec 2023 16:51:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 15 Dec 2023 16:51:03 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , , , , , Jeffrey Kardatzke , Jason-ch Chen , Johnson Wang , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung Subject: [PATCH v2 2/3] mailbox: mtk-cmdq: Sort cmdq platform data by compatible name Date: Fri, 15 Dec 2023 15:00:25 +0800 Message-ID: <20231215070026.2507-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231215070026.2507-1-jason-jh.lin@mediatek.com> References: <20231215070026.2507-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sort cmdq platform data according to the number sequence of compatible names. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 16c504f8d9d5..39bf066d376e 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -706,6 +706,13 @@ static const struct dev_pm_ops cmdq_pm_ops =3D { cmdq_runtime_resume, NULL) }; =20 +static const struct gce_plat gce_plat_mt6779 =3D { + .thread_nr =3D 24, + .shift =3D 3, + .control_by_sw =3D false, + .gce_num =3D 1 +}; + static const struct gce_plat gce_plat_mt8173 =3D { .thread_nr =3D 16, .shift =3D 0, @@ -720,10 +727,11 @@ static const struct gce_plat gce_plat_mt8183 =3D { .gce_num =3D 1 }; =20 -static const struct gce_plat gce_plat_mt6779 =3D { +static const struct gce_plat gce_plat_mt8186 =3D { .thread_nr =3D 24, .shift =3D 3, - .control_by_sw =3D false, + .control_by_sw =3D true, + .sw_ddr_en =3D true, .gce_num =3D 1 }; =20 @@ -741,19 +749,11 @@ static const struct gce_plat gce_plat_mt8195 =3D { .gce_num =3D 2 }; =20 -static const struct gce_plat gce_plat_mt8186 =3D { - .thread_nr =3D 24, - .shift =3D 3, - .control_by_sw =3D true, - .sw_ddr_en =3D true, - .gce_num =3D 1 -}; - static const struct of_device_id cmdq_of_ids[] =3D { + {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_mt677= 9}, {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_mt817= 3}, {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_mt818= 3}, {.compatible =3D "mediatek,mt8186-gce", .data =3D (void *)&gce_plat_mt818= 6}, - {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_mt677= 9}, {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_mt819= 2}, {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_mt819= 5}, {} --=20 2.18.0