From nobody Wed Nov 13 02:23:17 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1627718AFB for ; Fri, 15 Dec 2023 08:51:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SUml5VQj" X-UUID: 14aada4a9b2711eeba30773df0976c77-20231215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v9t/F+JMbwDsMpqLtuEY4uCI2C3pHq7TrRCe+nmUuRU=; b=SUml5VQjVLcFhg/gUBUlMaWawwgAPNBQGaea+EthLCsKtF2tdqb7JkTPVWX1sxseiVc38FUEi/KXpLc/2U1l+JTkJm/H7vZakvxE5WOQeN1a7HWd0IIJrB15GhgxzWz7eHHLCu/oQRgawBMDD2UypgtGiGK1ZYrm3gc9QcsLHmk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:46c75acb-6c41-4f01-a947-42767b5ca89f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:856bb5fd-4a48-46e2-b946-12f04f20af8c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 14aada4a9b2711eeba30773df0976c77-20231215 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 542733226; Fri, 15 Dec 2023 16:51:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 15 Dec 2023 16:51:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 15 Dec 2023 16:51:03 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , , , , , Jeffrey Kardatzke , Jason-ch Chen , Johnson Wang , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung Subject: [PATCH v2 1/3] mailbox: mtk-cmdq: Rename gce_plat variable with SoC name postfix Date: Fri, 15 Dec 2023 15:00:24 +0800 Message-ID: <20231215070026.2507-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231215070026.2507-1-jason-jh.lin@mediatek.com> References: <20231215070026.2507-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename gce_plat variable postfix from 'v1~v7' to SoC names. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index de862e9137d5..16c504f8d9d5 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -706,42 +706,42 @@ static const struct dev_pm_ops cmdq_pm_ops =3D { cmdq_runtime_resume, NULL) }; =20 -static const struct gce_plat gce_plat_v2 =3D { +static const struct gce_plat gce_plat_mt8173 =3D { .thread_nr =3D 16, .shift =3D 0, .control_by_sw =3D false, .gce_num =3D 1 }; =20 -static const struct gce_plat gce_plat_v3 =3D { +static const struct gce_plat gce_plat_mt8183 =3D { .thread_nr =3D 24, .shift =3D 0, .control_by_sw =3D false, .gce_num =3D 1 }; =20 -static const struct gce_plat gce_plat_v4 =3D { +static const struct gce_plat gce_plat_mt6779 =3D { .thread_nr =3D 24, .shift =3D 3, .control_by_sw =3D false, .gce_num =3D 1 }; =20 -static const struct gce_plat gce_plat_v5 =3D { +static const struct gce_plat gce_plat_mt8192 =3D { .thread_nr =3D 24, .shift =3D 3, .control_by_sw =3D true, .gce_num =3D 1 }; =20 -static const struct gce_plat gce_plat_v6 =3D { +static const struct gce_plat gce_plat_mt8195 =3D { .thread_nr =3D 24, .shift =3D 3, .control_by_sw =3D true, .gce_num =3D 2 }; =20 -static const struct gce_plat gce_plat_v7 =3D { +static const struct gce_plat gce_plat_mt8186 =3D { .thread_nr =3D 24, .shift =3D 3, .control_by_sw =3D true, @@ -750,12 +750,12 @@ static const struct gce_plat gce_plat_v7 =3D { }; =20 static const struct of_device_id cmdq_of_ids[] =3D { - {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_v2}, - {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_v3}, - {.compatible =3D "mediatek,mt8186-gce", .data =3D (void *)&gce_plat_v7}, - {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_v4}, - {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_v5}, - {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_v6}, + {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_mt817= 3}, + {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_mt818= 3}, + {.compatible =3D "mediatek,mt8186-gce", .data =3D (void *)&gce_plat_mt818= 6}, + {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_mt677= 9}, + {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_mt819= 2}, + {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_mt819= 5}, {} }; =20 --=20 2.18.0