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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id v6-20020a2e2f06000000b002c9f939598csm2184518ljv.70.2023.12.14.16.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 16:01:15 -0800 (PST) From: Konrad Dybcio Date: Fri, 15 Dec 2023 01:01:08 +0100 Subject: [PATCH 1/3] arm64: dts: qcom: sm6375: Hook up MPM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231215-topic-mpm_dt-v1-1-c6636fc75ce3@linaro.org> References: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> In-Reply-To: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Add a node for MPM and wire it up on consumers that use it. This also fixes a very bad and sad assumption I made when initially porting this SoC that the downstream MPM-TLMM mappings were 1-1. That apparently changed some time ago, so with this patch the MPM consumers will actually be hooked up to the correct interrupt lines. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 41 ++++++++++++++++++++++++++++++--= ---- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qco= m/sm6375.dtsi index 331bd98dbfde..7ac8bf26dda3 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -311,6 +311,25 @@ scm { }; }; =20 + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <5 296>, /* Soundwire wake_irq */ + <12 422>, /* DWC3 ss_phy_irq */ + <86 183>, /* MPM wake, SPMI */ + <89 314>, /* TSENS0 0C */ + <90 315>, /* TSENS1 0C */ + <93 164>, /* DWC3 dm_hs_phy_irq */ + <94 165>; /* DWC3 dp_hs_phy_irq */ + }; + memory@80000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -486,6 +505,7 @@ CPU_PD7: power-domain-cpu7 { =20 CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; + power-domains =3D <&mpm>; domain-idle-states =3D <&CLUSTER_SLEEP_0>; }; }; @@ -808,7 +828,7 @@ tlmm: pinctrl@500000 { reg =3D <0 0x00500000 0 0x800000>; interrupts =3D ; gpio-ranges =3D <&tlmm 0 0 157>; - /* TODO: Hook up MPM as wakeup-parent when it's there */ + wakeup-parent =3D <&mpm>; interrupt-controller; gpio-controller; #interrupt-cells =3D <2>; @@ -960,7 +980,7 @@ spmi_bus: spmi@1c40000 { <0 0x01c0a000 0 0x26000>; reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names =3D "periph_irq"; - interrupts =3D ; + interrupts-extended =3D <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; qcom,ee =3D <0>; qcom,channel =3D <0>; #address-cells =3D <2>; @@ -992,8 +1012,15 @@ tsens1: thermal-sensor@4413000 { }; =20 rpm_msg_ram: sram@45f0000 { - compatible =3D "qcom,rpm-msg-ram"; + compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; reg =3D <0 0x045f0000 0 0x7000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x045f0000 0x7000>; + + apss_mpm: sram@1b8 { + reg =3D <0x1b8 0x48>; + }; }; =20 sram@4690000 { @@ -1403,10 +1430,10 @@ usb_1: usb@4ef8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates =3D <19200000>, <133333333>; =20 - interrupts =3D , - , - , - ; + interrupts-extended =3D <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 12 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 93 IRQ_TYPE_EDGE_BOTH>, + <&mpm 94 IRQ_TYPE_EDGE_BOTH>; interrupt-names =3D "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", --=20 2.40.1 From nobody Sat Dec 27 22:53:10 2025 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C4D319474 for ; Fri, 15 Dec 2023 00:01:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id v6-20020a2e2f06000000b002c9f939598csm2184518ljv.70.2023.12.14.16.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 16:01:16 -0800 (PST) From: Konrad Dybcio Date: Fri, 15 Dec 2023 01:01:09 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: msm8996: Hook up MPM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231215-topic-mpm_dt-v1-2-c6636fc75ce3@linaro.org> References: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> In-Reply-To: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Wire up MPM and the interrupts it provides. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 39 +++++++++++++++++++++++++++++--= ---- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index 35a0d2a69711..11e3fe4f342f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -444,6 +444,25 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <2 184>, /* TSENS1 upper_lower_int */ + <52 243>, /* DWC3_PRI ss_phy_irq */ + <79 347>, /* DWC3_PRI hs_phy_irq */ + <80 352>, /* DWC3_SEC hs_phy_irq */ + <81 347>, /* QUSB2_PHY_PRI DP+DM */ + <82 352>, /* QUSB2_PHY_SEC DP+DM */ + <87 326>; /* SPMI */ + }; + psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; @@ -733,8 +752,15 @@ pciephy_2: phy@3000 { }; =20 rpm_msg_ram: sram@68000 { - compatible =3D "qcom,rpm-msg-ram"; + compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; reg =3D <0x00068000 0x6000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x00068000 0x7000>; + + apss_mpm: sram@1b8 { + reg =3D <0x1b8 0x48>; + }; }; =20 qfprom@74000 { @@ -820,8 +846,8 @@ tsens1: thermal-sensor@4ad000 { reg =3D <0x004ad000 0x1000>, /* TM */ <0x004ac000 0x1000>; /* SROT */ #qcom,sensors =3D <8>; - interrupts =3D , - ; + interrupts-extended =3D <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "uplow", "critical"; #thermal-sensor-cells =3D <1>; }; @@ -1343,6 +1369,7 @@ tlmm: pinctrl@1010000 { interrupts =3D ; gpio-controller; gpio-ranges =3D <&tlmm 0 0 150>; + wakeup-parent =3D <&mpm>; #gpio-cells =3D <2>; interrupt-controller; #interrupt-cells =3D <2>; @@ -1870,7 +1897,7 @@ spmi_bus: spmi@400f000 { <0x0400a000 0x002100>; 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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id v6-20020a2e2f06000000b002c9f939598csm2184518ljv.70.2023.12.14.16.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 16:01:18 -0800 (PST) From: Konrad Dybcio Date: Fri, 15 Dec 2023 01:01:10 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: qcm2290: Hook up MPM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231215-topic-mpm_dt-v1-3-c6636fc75ce3@linaro.org> References: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> In-Reply-To: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Wire up MPM and the interrupts it provides. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 42 +++++++++++++++++++++++++++++--= ---- 1 file changed, 35 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qc= om/qcm2290.dtsi index ce04d0acdede..0911fb08ed63 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -199,6 +199,7 @@ CPU_PD3: power-domain-cpu3 { =20 CLUSTER_PD: power-domain-cpu-cluster { #power-domain-cells =3D <0>; + power-domains =3D <&mpm>; domain-idle-states =3D <&CLUSTER_SLEEP>; }; }; @@ -266,6 +267,24 @@ rpmpd_opp_turbo_plus: opp8 { }; }; }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <2 275>, /* TSENS0 uplow */ + <5 296>, /* Soundwire master_irq */ + <12 422>, /* DWC3 ss_phy_irq */ + <24 79>, /* Soundwire wake_irq */ + <86 183>, /* MPM wake, SPMI */ + <90 260>; /* QUSB2_PHY DP+DM */ + }; }; =20 reserved_memory: reserved-memory { @@ -429,6 +448,7 @@ tlmm: pinctrl@500000 { interrupts =3D ; gpio-controller; gpio-ranges =3D <&tlmm 0 0 127>; + wakeup-parent =3D <&mpm>; #gpio-cells =3D <2>; interrupt-controller; #interrupt-cells =3D <2>; @@ -778,7 +798,7 @@ spmi_bus: spmi@1c40000 { "obsrvr", "intr", "cnfg"; - interrupts =3D ; + interrupts-extended =3D <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "periph_irq"; qcom,ee =3D <0>; qcom,channel =3D <0>; @@ -793,8 +813,8 @@ tsens0: thermal-sensor@4411000 { reg =3D <0x0 0x04411000 0x0 0x1ff>, <0x0 0x04410000 0x0 0x8>; #qcom,sensors =3D <10>; - interrupts =3D , - ; + interrupts-extended =3D <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "uplow", "critical"; #thermal-sensor-cells =3D <1>; }; @@ -813,8 +833,15 @@ bimc: interconnect@4480000 { }; =20 rpm_msg_ram: sram@45f0000 { - compatible =3D "qcom,rpm-msg-ram"; + compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; reg =3D <0x0 0x045f0000 0x0 0x7000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x045f0000 0x7000>; + + apss_mpm: sram@1b8 { + reg =3D <0x1b8 0x48>; + }; }; =20 sram@4690000 { @@ -1293,9 +1320,10 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, usb: usb@4ef8800 { compatible =3D "qcom,qcm2290-dwc3", "qcom,dwc3"; reg =3D <0x0 0x04ef8800 0x0 0x400>; - interrupts =3D , - ; - interrupt-names =3D "hs_phy_irq", "ss_phy_irq"; + interrupts-extended =3D <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hs_phy_irq", + "ss_phy_irq"; =20 clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, --=20 2.40.1