From nobody Fri Dec 19 00:27:42 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A06B720305 for ; Fri, 15 Dec 2023 10:32:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="WkGmsWB6" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3364a1451c6so247129f8f.3 for ; Fri, 15 Dec 2023 02:32:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1702636330; x=1703241130; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w3bsA3Hq1tZST6LLgdgUCasdE4/LKtqWt/9/psp4mcs=; b=WkGmsWB6mErIuSPKRgwJk99QrrPKhdO4xeWDYJi8dCV8BSsfLGzVH0a0IIWPJuNV20 rGJ8eIZ37dboX9DG4b3t97m6+rnqUl+Ex6i9fU1AwD5rFENzDsuOlkNJimpjP0wndB8w sN0rLED3t4GM8+/h66lycMs0PHsj2AVEOBmIQYe/+wtcDtvkY0cvZ/SiT4tUGanHvCjX ZeASR51Qs4T78kqVuPMODnrVGABn0OqnoTkAi4JuTj0DbtGhgfAcOseTDA4UikT6Klnb 5Agp4w7Y1BBw9vD9dPDVqWVRrAutmpSwXA10I37AHw38A5wgFKY7mU1Xj6gnhFN7K5uH kAHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702636330; x=1703241130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w3bsA3Hq1tZST6LLgdgUCasdE4/LKtqWt/9/psp4mcs=; b=h0nPiUB73+SNirmcL5/zfcB3tkaVaIBSWgbfPMXhzR2uDG+XYtTsmHcFlvpgHhvJmo zl00tDrB+9wdWoO7Jk4Bq0qc9IxGpORrBnwAHZR7ov1slDq5/tAyGWdrNm4oDnQqGkvT TGV7dcOm1gYpizHjeq1H3n3z3KkpJllDX36e6+7rCLjY2OAD5VcOsIUlbrwpS+Nw4Ngd VVibeOZuQJEMeN5mui6cllQANdaGD+695Oy4DvXXZgVfEaYzvkhXsynrPlsarA4BTqNX zAYyWFfeJ2n+rWMeOfc6jxceuzLkmTCDrSUiqATmyrheMKrADHIytVJqmMDuO/+0TPzX 3FqQ== X-Gm-Message-State: AOJu0YwuqX42+ujbArl+VlO3oVRFaWfwCiImQ8GBu5C9hsci/TcWnulA SPr8K2Sg8K333CfIb9z6ZYgIiWLKbl3xTyoeUbn2Yg== X-Google-Smtp-Source: AGHT+IGe4MMucKjjA3WOJtoTmJMh3Fj4pIUjOpDhgEcF23Hnh5z6vn2Zy3FUjhpnZwv0L/I4CQkvqw== X-Received: by 2002:adf:ebc4:0:b0:333:2fd2:8146 with SMTP id v4-20020adfebc4000000b003332fd28146mr7175355wrn.99.1702636330773; Fri, 15 Dec 2023 02:32:10 -0800 (PST) Received: from localhost.localdomain (abordeaux-655-1-152-60.w90-5.abo.wanadoo.fr. [90.5.9.60]) by smtp.gmail.com with ESMTPSA id q11-20020adffecb000000b003332db7d91dsm18421015wrs.39.2023.12.15.02.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 02:32:10 -0800 (PST) From: David Lechner To: linux-iio@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Cc: David Lechner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Liam Girdwood , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: spi: add spi-rx-bus-channels peripheral property Date: Fri, 15 Dec 2023 04:32:02 -0600 Message-Id: <20231215-ad7380-mainline-v3-1-7a11ebf642b9@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> References: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.12.4 Content-Transfer-Encoding: quoted-printable This adds a new spi-rx-bus-channels property to the generic spi peripheral property bindings. This property is used to describe devices that have parallel data output channels. This property is different from spi-rx-bus-width in that the latter means that we are reading multiple bits of a single word at one time while the former means that we are reading single bits of multiple words at the same time. Signed-off-by: David Lechner Reviewed-by: Rob Herring --- The rest of this series is ready to merge, so just looking for an ack from Mark on this one. .../devicetree/bindings/spi/spi-peripheral-props.yaml | 12 ++++++++= ++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 15938f81fdce..1c8e71c18234 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -67,6 +67,18 @@ properties: enum: [0, 1, 2, 4, 8] default: 1 =20 + spi-rx-bus-channels: + description: + The number of parallel channels for read transfers. The difference b= etween + this and spi-rx-bus-width is that a value N for spi-rx-bus-channels = means + the SPI bus is receiving one bit each of N different words at the sa= me + time whereas a value M for spi-rx-bus-width means that the bus is + receiving M bits of a single word at the same time. It is also possi= ble to + use both properties at the same time, meaning the bus is receiving M= bits + of N different words at the same time. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. --=20 2.34.1 From nobody Fri Dec 19 00:27:42 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74325208BD for ; Fri, 15 Dec 2023 10:32:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="n2SUDFzs" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-33642ab735dso361819f8f.0 for ; Fri, 15 Dec 2023 02:32:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1702636331; x=1703241131; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f0vxSZ9RvxjYOzxMLTC82yIpjyAij/ySbPoNuVAOnVc=; b=n2SUDFzs4UsriIJm0d/7roV2+AaFTVoW98MhnZiSZg9+ssNWei5VX8kgAlvri5zwF+ li4QQR4RgojWhik9zpvi0/Hk/TXcbG1xSm0xU1v7f9pkYXlKqQ1MJDh+1yn6SAgdkrFG ML8k7esu33UZvQv7ZaXb0GHT7CQmm/viiquVZH5ISdaI2KI1nGGds6ZmZfEGVMK/83Pk P9hamtZNSPwH7HKNmbochwwcHYjbRMAY3+e6yDDRU7OvRXIdh0l6HRCVs+HxneKC4R9L hZLMpFIvH7LWhzWFw9UDSYv7icNwGnAlgealQL1KsYsuZ9H4BCgibynOqSL7v1QiPPD2 pUGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702636331; x=1703241131; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f0vxSZ9RvxjYOzxMLTC82yIpjyAij/ySbPoNuVAOnVc=; b=nwIPuHcoSKgKr/jC5E0r0X4nvJvzY2UCB/LtwtFf0kUoBOJIfw0/ZbDFQRGA0wLkZf dFcdLxqB4f98AvT9vDP1ve4FlHiqac9g4AKnCHSg0IaspYzEMSoVvizY5sUQjSVQgAvo lzdJ6qF5D27kNllJHs9jVm7lKURWvBUktu5nyUhMgOpQ6/lprcdAyPcJ5gZZx4qWDL8Z ZzXmB+6t0THLANSgWa/r0beSsKb9blMkOx7NvTCwL936HvdZJ1PaSvPrOC+DZom0Hr38 2dbM3JkYTZdss82w8xRhRr0rr75QQVQpVQJXkloEZqyu6uKy0pAmtcLOVPxEdJtu6f7C 9o0w== X-Gm-Message-State: AOJu0YznXF/JWj02zKsRF+Ec7Vq7ohZhBdkF2iYF+X5qmUNI/0gtyaML /L3fuKBTHEVsiNegkr+OMhb78w== X-Google-Smtp-Source: AGHT+IEOOzxRXGV1KZ0ZURPlNdzksXFIi0QgWxDIMIyw6Tr1CG06Vcl6zRkqiJlkf7gxnqX8FFeMAA== X-Received: by 2002:a5d:430d:0:b0:333:130d:4311 with SMTP id h13-20020a5d430d000000b00333130d4311mr2749859wrq.52.1702636331594; Fri, 15 Dec 2023 02:32:11 -0800 (PST) Received: from localhost.localdomain (abordeaux-655-1-152-60.w90-5.abo.wanadoo.fr. [90.5.9.60]) by smtp.gmail.com with ESMTPSA id q11-20020adffecb000000b003332db7d91dsm18421015wrs.39.2023.12.15.02.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 02:32:11 -0800 (PST) From: David Lechner To: linux-iio@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Cc: David Lechner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Liam Girdwood , Mark Brown , linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v3 2/3] dt-bindings: iio: adc: Add binding for AD7380 ADCs Date: Fri, 15 Dec 2023 04:32:03 -0600 Message-Id: <20231215-ad7380-mainline-v3-2-7a11ebf642b9@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> References: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.12.4 Content-Transfer-Encoding: quoted-printable This adds a binding specification for the Analog Devices Inc. AD7380 family of ADCs. Reviewed-by: Conor Dooley Signed-off-by: David Lechner --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 107 +++++++++++++++++= ++++ MAINTAINERS | 9 ++ 2 files changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml new file mode 100644 index 000000000000..43d58c52f7dd --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7380.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices Simultaneous Sampling Analog to Digital Converters + +maintainers: + - Michael Hennerich + - Nuno S=C3=A1 + +description: | + * https://www.analog.com/en/products/ad7380.html + * https://www.analog.com/en/products/ad7381.html + * https://www.analog.com/en/products/ad7383.html + * https://www.analog.com/en/products/ad7384.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + - adi,ad7383 + - adi,ad7384 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 80000000 + spi-cpol: true + spi-cpha: true + + spi-rx-bus-channels: + description: + In 1-wire mode, the SDOA pin acts as the sole data line and the SDOB= /ALERT + pin acts as the ALERT interrupt signal. In 2-wire mode, data for inp= ut A + is read from SDOA and data for input B is read from SDOB/ALERT (and = the + ALERT interrupt signal is not available). + enum: [1, 2] + + vcc-supply: + description: A 3V to 3.6V supply that powers the chip. + + vlogic-supply: + description: + A 1.65V to 3.6V supply for the logic pins. + + refio-supply: + description: + A 2.5V to 3.3V supply for the external reference voltage. When omitt= ed, + the internal 2.5V reference is used. + + interrupts: + description: + When the device is using 1-wire mode, this property is used to optio= nally + specify the ALERT interrupt. + maxItems: 1 + +required: + - compatible + - reg + - vcc-supply + - vlogic-supply + +allOf: + - if: + required: + - spi-rx-bus-channels + then: + if: + properties: + spi-rx-bus-channels: + const: 2 + then: + properties: + interrupts: false + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7380"; + reg =3D <0>; + + spi-cpol; + spi-cpha; + spi-max-frequency =3D <80000000>; + + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpio0>; + + vcc-supply =3D <&supply_3_3V>; + vlogic-supply =3D <&supply_3_3V>; + refio-supply =3D <&supply_2_5V>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fe1f6f97f96a..e2a998be5879 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -430,6 +430,15 @@ W: http://wiki.analog.com/AD7142 W: https://ez.analog.com/linux-software-drivers F: drivers/input/misc/ad714x.c =20 +AD738X ADC DRIVER (AD7380/1/2/4) +M: Michael Hennerich +M: Nuno S=C3=A1 +R: David Lechner +S: Supported +W: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/= ad738x +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml + AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich S: Supported --=20 2.34.1 From nobody Fri Dec 19 00:27:42 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 456DE249EF for ; Fri, 15 Dec 2023 10:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="fXfm67lP" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-32f8441dfb5so392199f8f.0 for ; Fri, 15 Dec 2023 02:32:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1702636332; x=1703241132; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cNUIgGKeBLNxRtZa/e62xwwjn2LbYij3IIZziGi/+Cs=; b=fXfm67lPjf1836o+7z3zuPoa6EUu3NdrzwC6Ty8UuPjrN8A54jd43E9peGszT9zLjv 2KF/xfCXUUrnTiOnr73VhgE0vdv8PsooT5wvVqZ8ZECHHu6R/NbCX2QzWfVjpU8pJSGW L8CgORvrgM63JM/u6LxgJ+2s2GUv0cT+VPG7nTi0ajFxnIFdxkSsCMGfz/8liC3Abeg5 I4VINI5UbKfoy8sfi4KFYi3AgCsk6Z6nFD/JDjZhvxMIaFgY6kVrundSeKqeM9y9Tvcv /Thx6kC2Pk5ovPLH2NdEg2lpnG/7E45NCM2Lw+0qaWAU2WRQVNTxyi6OMkOjRvU9NO2L bCOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702636332; x=1703241132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cNUIgGKeBLNxRtZa/e62xwwjn2LbYij3IIZziGi/+Cs=; b=Q7yT4w6ld45QP12MiPubemDGhUM3BHe9A7JCdRuWGQ9+lFKK93DsIAI2TxPF4suXFD Lz7V04cZoosmN5mSF7jVCGqQ9Hs1GaLPSeCxPv/yf0zq8dFMOk/gsaRIerMna81zZV/a F1yMiO49JOVtaaVBfWF1R5DRV2IW8r5N1SEJz7Bnh1dHGQtpnJbX1+GS54kDXCIOrc6I dm9NzlG4EaM7eGwwqIIV84drwUiSG08sKe87djkVqCXzEr7vO1pr3FDGQyMgYhIebv3+ fU0a1vKYlFLdh64mLXJeWt/AZC5INKq0Z7e5jLmzvTAsSQ5EFxkL877OFpzKGhuAe+HF h0XQ== X-Gm-Message-State: AOJu0YwS0vd873R6ng7RivHA3jR+NHEFGC/jTfoS5vF62n4ICMfR2ss1 Q3/j8Koci7oGvRoiDnERMi9VDA== X-Google-Smtp-Source: AGHT+IFeLk1CnSx2XUPLfPx2pcI54txed0kAOP+Eqa42CkBqPcmuy7REMQGvvG1qqQUTnteXdhO+OA== X-Received: by 2002:adf:e28e:0:b0:334:b3d0:c300 with SMTP id v14-20020adfe28e000000b00334b3d0c300mr6228671wri.32.1702636332422; Fri, 15 Dec 2023 02:32:12 -0800 (PST) Received: from localhost.localdomain (abordeaux-655-1-152-60.w90-5.abo.wanadoo.fr. [90.5.9.60]) by smtp.gmail.com with ESMTPSA id q11-20020adffecb000000b003332db7d91dsm18421015wrs.39.2023.12.15.02.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 02:32:12 -0800 (PST) From: David Lechner To: linux-iio@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Cc: David Lechner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Liam Girdwood , Mark Brown , linux-kernel@vger.kernel.org, Stefan Popa Subject: [PATCH v3 3/3] iio: adc: ad7380: new driver for AD7380 ADCs Date: Fri, 15 Dec 2023 04:32:04 -0600 Message-Id: <20231215-ad7380-mainline-v3-3-7a11ebf642b9@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> References: <20231215-ad7380-mainline-v3-0-7a11ebf642b9@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.12.4 Content-Transfer-Encoding: quoted-printable This adds a new driver for the AD7380 family ADCs. The driver currently implements basic support for the AD7380, AD7381, AD7383, and AD7384 2-channel differential ADCs. Support for additional single-ended and 4-channel chips that use the same register map as well as additional features of the chip will be added in future patches. Co-developed-by: Stefan Popa Signed-off-by: Stefan Popa Reviewed-by: Nuno Sa Signed-off-by: David Lechner --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 16 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7380.c | 462 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 480 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e2a998be5879..5a54620a31b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -438,6 +438,7 @@ S: Supported W: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/= ad738x W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +F: drivers/iio/adc/ad7380.c =20 AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 35f9867da12c..cbfd626712e3 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -122,6 +122,22 @@ config AD7298 To compile this driver as a module, choose M here: the module will be called ad7298. =20 +config AD7380 + tristate "Analog Devices AD7380 ADC driver" + depends on SPI_MASTER + select IIO_BUFFER + select IIO_TRIGGER + select IIO_TRIGGERED_BUFFER + help + AD7380 is a family of simultaneous sampling ADCs that share the same + SPI register map and have similar pinouts. + + Say yes here to build support for Analog Devices AD7380 ADC and + similar chips. + + To compile this driver as a module, choose M here: the module will be + called ad7380. + config AD7476 tristate "Analog Devices AD7476 1-channel ADCs driver and other similar d= evices from AD and TI" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index bee11d442af4..9c921c497655 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_AD7291) +=3D ad7291.o obj-$(CONFIG_AD7292) +=3D ad7292.o obj-$(CONFIG_AD7298) +=3D ad7298.o obj-$(CONFIG_AD7923) +=3D ad7923.o +obj-$(CONFIG_AD7380) +=3D ad7380.o obj-$(CONFIG_AD7476) +=3D ad7476.o obj-$(CONFIG_AD7606_IFACE_PARALLEL) +=3D ad7606_par.o obj-$(CONFIG_AD7606_IFACE_SPI) +=3D ad7606_spi.o diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c new file mode 100644 index 000000000000..80712aaa9548 --- /dev/null +++ b/drivers/iio/adc/ad7380.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD738x Simultaneous Sampling SAR ADCs + * + * Copyright 2017 Analog Devices Inc. + * Copyright 2023 BayLibre, SAS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* 2.5V internal reference voltage */ +#define AD7380_INTERNAL_REF_MV 2500 + +/* reading and writing registers is more reliable at lower than max speed = */ +#define AD7380_REG_WR_SPEED_HZ 10000000 + +#define AD7380_REG_WR BIT(15) +#define AD7380_REG_REGADDR GENMASK(14, 12) +#define AD7380_REG_DATA GENMASK(11, 0) + +#define AD7380_REG_ADDR_NOP 0x0 +#define AD7380_REG_ADDR_CONFIG1 0x1 +#define AD7380_REG_ADDR_CONFIG2 0x2 +#define AD7380_REG_ADDR_ALERT 0x3 +#define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 +#define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 + +#define AD7380_CONFIG1_OS_MODE BIT(9) +#define AD7380_CONFIG1_OSR GENMASK(8, 6) +#define AD7380_CONFIG1_CRC_W BIT(5) +#define AD7380_CONFIG1_CRC_R BIT(4) +#define AD7380_CONFIG1_ALERTEN BIT(3) +#define AD7380_CONFIG1_RES BIT(2) +#define AD7380_CONFIG1_REFSEL BIT(1) +#define AD7380_CONFIG1_PMODE BIT(0) + +#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) +#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_RESET GENMASK(7, 0) + +#define AD7380_CONFIG2_RESET_SOFT 0x3C +#define AD7380_CONFIG2_RESET_HARD 0xFF + +#define AD7380_ALERT_LOW_TH GENMASK(11, 0) +#define AD7380_ALERT_HIGH_TH GENMASK(11, 0) + +struct ad7380_chip_info { + const char *name; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +#define AD7380_DIFFERENTIAL_CHANNEL(index, bits) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .indexed =3D 1, \ + .differential =3D 1, \ + .channel =3D 2 * (index), \ + .channel2 =3D 2 * (index) + 1, \ + .scan_index =3D (index), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D (bits), \ + .storagebits =3D 16, \ + .endianness =3D IIO_CPU, \ + }, \ +} + +#define DEFINE_AD7380_DIFFERENTIAL_2_CHANNEL(name, bits) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_DIFFERENTIAL_CHANNEL(0, bits), \ + AD7380_DIFFERENTIAL_CHANNEL(1, bits), \ + IIO_CHAN_SOFT_TIMESTAMP(2), \ +} + +/* fully differential */ +DEFINE_AD7380_DIFFERENTIAL_2_CHANNEL(ad7380_channels, 16); +DEFINE_AD7380_DIFFERENTIAL_2_CHANNEL(ad7381_channels, 14); +/* pseudo differential */ +DEFINE_AD7380_DIFFERENTIAL_2_CHANNEL(ad7383_channels, 16); +DEFINE_AD7380_DIFFERENTIAL_2_CHANNEL(ad7384_channels, 14); + +/* Since this is simultaneous sampling, we don't allow individual channels= . */ +static const unsigned long ad7380_2_channel_scan_masks[] =3D { + GENMASK(1, 0), + 0 +}; + +static const struct ad7380_chip_info ad7380_chip_info =3D { + .name =3D "ad7380", + .channels =3D ad7380_channels, + .num_channels =3D ARRAY_SIZE(ad7380_channels), +}; + +static const struct ad7380_chip_info ad7381_chip_info =3D { + .name =3D "ad7381", + .channels =3D ad7381_channels, + .num_channels =3D ARRAY_SIZE(ad7381_channels), +}; + +static const struct ad7380_chip_info ad7383_chip_info =3D { + .name =3D "ad7383", + .channels =3D ad7383_channels, + .num_channels =3D ARRAY_SIZE(ad7383_channels), +}; + +static const struct ad7380_chip_info ad7384_chip_info =3D { + .name =3D "ad7384", + .channels =3D ad7384_channels, + .num_channels =3D ARRAY_SIZE(ad7384_channels), +}; + +struct ad7380_state { + const struct ad7380_chip_info *chip_info; + struct spi_device *spi; + struct regulator *vref; + struct regmap *regmap; + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + * Make the buffer large enough for 2 16-bit samples and one 64-bit + * aligned 64 bit timestamp. + */ + struct { + u16 raw[2]; + s64 ts __aligned(8); + } scan_data __aligned(IIO_DMA_MINALIGN); + u16 tx[2]; + u16 rx[2]; +}; + +static int ad7380_regmap_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ad7380_state *st =3D context; + struct spi_transfer xfer =3D { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .tx_buf =3D &st->tx[0], + }; + + st->tx[0] =3D FIELD_PREP(AD7380_REG_WR, 1) | + FIELD_PREP(AD7380_REG_REGADDR, reg) | + FIELD_PREP(AD7380_REG_DATA, val); + + return spi_sync_transfer(st->spi, &xfer, 1); +} + +static int ad7380_regmap_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ad7380_state *st =3D context; + struct spi_transfer xfers[] =3D { + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .tx_buf =3D &st->tx[0], + .cs_change =3D 1, + .cs_change_delay =3D { + .value =3D 10, /* t[CSH] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + }, { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .rx_buf =3D &st->rx[0], + }, + }; + int ret; + + st->tx[0] =3D FIELD_PREP(AD7380_REG_WR, 0) | + FIELD_PREP(AD7380_REG_REGADDR, reg) | + FIELD_PREP(AD7380_REG_DATA, 0); + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret < 0) + return ret; + + *val =3D FIELD_GET(AD7380_REG_DATA, st->rx[0]); + + return 0; +} + +const struct regmap_config ad7380_regmap_config =3D { + .reg_bits =3D 3, + .val_bits =3D 12, + .reg_read =3D ad7380_regmap_reg_read, + .reg_write =3D ad7380_regmap_reg_write, + .max_register =3D AD7380_REG_ADDR_ALERT_HIGH_TH, + .can_sleep =3D true, +}; + +static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, + u32 writeval, u32 *readval) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + if (readval) + ret =3D regmap_read(st->regmap, reg, readval); + else + ret =3D regmap_write(st->regmap, reg, writeval); + + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static irqreturn_t ad7380_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_transfer xfer =3D { + .bits_per_word =3D st->chip_info->channels[0].scan_type.realbits, + .len =3D 4, + .rx_buf =3D st->scan_data.raw, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + goto out; + + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data, + pf->timestamp); + +out: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int ad7380_read_direct(struct ad7380_state *st, + struct iio_chan_spec const *chan, int *val) +{ + struct spi_transfer xfers[] =3D { + /* toggle CS (no data xfer) to trigger a conversion */ + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D chan->scan_type.realbits, + .delay =3D { + .value =3D 190, /* t[CONVERT] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + .cs_change =3D 1, + .cs_change_delay =3D { + .value =3D 10, /* t[CSH] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + }, + /* then read both channels */ + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D chan->scan_type.realbits, + .rx_buf =3D &st->rx[0], + .len =3D 4, + }, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret < 0) + return ret; + + *val =3D sign_extend32(st->rx[chan->scan_index], + chan->scan_type.realbits - 1); + + return IIO_VAL_INT; +} + +static int ad7380_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret; + + switch (info) { + case IIO_CHAN_INFO_RAW: + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D ad7380_read_direct(st, chan, val); + iio_device_release_direct_mode(indio_dev); + + return ret; + case IIO_CHAN_INFO_SCALE: + if (st->vref) { + ret =3D regulator_get_voltage(st->vref); + if (ret < 0) + return ret; + + *val =3D ret / 1000; + } else { + *val =3D AD7380_INTERNAL_REF_MV; + } + + *val2 =3D chan->scan_type.realbits; + + return IIO_VAL_FRACTIONAL_LOG2; + } + + return -EINVAL; +} + +static const struct iio_info ad7380_info =3D { + .read_raw =3D &ad7380_read_raw, + .debugfs_reg_access =3D &ad7380_debugfs_reg_access, +}; + +static int ad7380_init(struct ad7380_state *st) +{ + int ret; + + /* perform hard reset */ + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_RESET, + FIELD_PREP(AD7380_CONFIG2_RESET, + AD7380_CONFIG2_RESET_HARD)); + if (ret < 0) + return ret; + + /* select internal or external reference voltage */ + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_REFSEL, + FIELD_PREP(AD7380_CONFIG1_REFSEL, !!st->vref)); + if (ret < 0) + return ret; + + /* SPI 1-wire mode */ + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_SDO, + FIELD_PREP(AD7380_CONFIG2_SDO, 1)); +} + +static void ad7380_regulator_disable(void *p) +{ + regulator_disable(p); +} + +static int ad7380_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct ad7380_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return dev_err_probe(&spi->dev, -EINVAL, "missing match data\n"); + + st->vref =3D devm_regulator_get_optional(&spi->dev, "refio"); + if (IS_ERR(st->vref)) { + /* + * If there is no REFIO supply, then it means that we are using + * the internal 2.5V reference. + */ + if (PTR_ERR(st->vref) =3D=3D -ENODEV) + st->vref =3D NULL; + else + return dev_err_probe(&spi->dev, PTR_ERR(st->vref), + "Failed to get refio regulator\n"); + } + + if (st->vref) { + ret =3D regulator_enable(st->vref); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&spi->dev, ad7380_regulator_disable, + st->vref); + if (ret) + return ret; + } + + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); + if (IS_ERR(st->regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), + "failed to allocate register map\n"); + + indio_dev->channels =3D st->chip_info->channels; + indio_dev->num_channels =3D st->chip_info->num_channels; + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad7380_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->available_scan_masks =3D ad7380_2_channel_scan_masks; + + ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + iio_pollfunc_store_time, + ad7380_trigger_handler, NULL); + if (ret) + return ret; + + ret =3D ad7380_init(st); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct of_device_id ad7380_of_match_table[] =3D { + { .compatible =3D "adi,ad7380", .data =3D &ad7380_chip_info }, + { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, + { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, + { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, + { } +}; + +static const struct spi_device_id ad7380_id_table[] =3D { + { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, + { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, + { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, + { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad7380_id_table); + +static struct spi_driver ad7380_driver =3D { + .driver =3D { + .name =3D "ad7380", + .of_match_table =3D ad7380_of_match_table, + }, + .probe =3D ad7380_probe, + .id_table =3D ad7380_id_table, +}; +module_spi_driver(ad7380_driver); + +MODULE_AUTHOR("Stefan Popa "); +MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1