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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id vq2-20020a170907a4c200b00a22faee6649sm2547776ejc.117.2023.12.14.05.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 05:10:22 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Abel Vesa Subject: [PATCH 2/4] arm64: dts: qcom: x1e80100: add Soundwire controllers Date: Thu, 14 Dec 2023 14:10:14 +0100 Message-Id: <20231214131016.30502-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> References: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes for LPASS Soundwire v2.0.0 controllers. Difference against SM8550: 1. Update port configs to match reference implementation, 2. LPASS TLMM GPIO14 is not used as WCD_SR_TX_DATA2 pin but as GPIO (camera). Cc: Abel Vesa Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 226 +++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 8bc6e544bbc9..262ff4700194 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2999,6 +2999,36 @@ lpass_wsa2macro: codec@6aa0000 { sound-name-prefix =3D "WSA2"; }; =20 + swr3: soundwire@6ab0000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ab0000 0 0x10000>; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + interrupts =3D ; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8= 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_rxmacro: codec@6ac0000 { compatible =3D "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-ma= cro"; reg =3D <0 0x06ac0000 0 0x1000>; @@ -3016,6 +3046,36 @@ lpass_rxmacro: codec@6ac0000 { #sound-dai-cells =3D <1>; }; =20 + swr1: soundwire@6ad0000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ad0000 0 0x10000>; + clocks =3D <&lpass_rxmacro>; + clock-names =3D "iface"; + interrupts =3D ; + label =3D "RX"; + + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; + + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_txmacro: codec@6ae0000 { compatible =3D "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-ma= cro"; reg =3D <0 0x06ae0000 0 0x1000>; @@ -3051,6 +3111,68 @@ lpass_wsamacro: codec@6b00000 { sound-name-prefix =3D "WSA"; }; =20 + swr0: soundwire@6b10000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06b10000 0 0x10000>; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + interrupts =3D ; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8= 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + swr2: soundwire@6d30000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06d30000 0 0x10000>; + clocks =3D <&lpass_txmacro>; + clock-names =3D "iface"; + interrupts =3D , + ; + interrupt-names =3D "core", "wakeup"; + label =3D "TX"; + + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <1>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_vamacro: codec@6d44000 { compatible =3D "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-ma= cro"; reg =3D <0 0x06d44000 0 0x1000>; @@ -3078,6 +3200,110 @@ lpass_tlmm: pinctrl@6e80000 { gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; }; =20 lpass_ag_noc: interconnect@7e40000 { --=20 2.34.1