From nobody Sat Dec 27 22:54:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9125AC4332F for ; Thu, 14 Dec 2023 13:10:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573219AbjLNNKU (ORCPT ); Thu, 14 Dec 2023 08:10:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573195AbjLNNKR (ORCPT ); Thu, 14 Dec 2023 08:10:17 -0500 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB0A011B for ; Thu, 14 Dec 2023 05:10:22 -0800 (PST) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a1f5cb80a91so936620666b.3 for ; Thu, 14 Dec 2023 05:10:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702559421; x=1703164221; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dj/xdv07DFvQtnBJiRse372jufWHWRedV/q2JB552Gw=; b=nTXdC07591BgP8o66euCQCNJUPSL1TSEJSnfQGJhwIpH/zxMcIagr46Kz9yMmvXsca PYUbqpJfUvdDbIDh7F8IRJTAgbzI5oR7ql3GJOVbQ8/BVM8z6wTyhCZBYrVY0w2Wq6gw tN4Z1gOfF87eb/hZsgAuPccMvrbH3S9kWetwNH6Lh1+XwFQf6u9aXpyfxTqPmlGR4DLp CHKpmMKR4celz5Fhj7q+JRHXVmPppOcPN22+hd12w+ZWFzCKOMENNqnfPFnK3VAMvYwG kPcnd7F/+a4xrbKyTkT5PaiYKOx+ySuZsku+f3/e2HfeJxSuSdl5HGEjYCpRN3Ymo0bV +vBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702559421; x=1703164221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dj/xdv07DFvQtnBJiRse372jufWHWRedV/q2JB552Gw=; b=DVXYk50MAM0v9giESjOFFY8R6PF1hdDhTKQGFlej7ZkTxQF/enV/UuHe4xLBJQJdVY jUIJlu2EiGA0+iOQ6oc7rQ1A1383OWkc70xxJFAdnk28m2DHEepCR9z6f98D8JOX20mz 87hpA9Q2+1LYYkUxa/NxSvcglC0fDEkUrgdVf64VCZp1DVgZU8YiyZUiA+fQxbptyDHC WY1ws740l7PlLiRqgUdsU+9aObZCBlP03UzeyYMZC3jQi5XUo0qtBOa+h+zOxlUSGr+n /i/M8fIwXZ6eyK7/tm2eFDxV2rw4EXQWvcD1nihwaZJa6zekQExO8TbzjhlP+fqf4Hp0 pNfw== X-Gm-Message-State: AOJu0YxsuD/vac6pbFA/8dTHCuZ6CTgVH2/d333NNdqc9lp2/YB4vcGn lzqPCBPYoow3PrCeDbnXZmqhQg== X-Google-Smtp-Source: AGHT+IE9v21JflqGlQeQvlZapXPuTSOiq+n0C6xc3Zp/62SYVeg6jgOoAVfQMHHbtA/BY10Zg+TeNA== X-Received: by 2002:a17:906:495a:b0:a1b:9f36:f37b with SMTP id f26-20020a170906495a00b00a1b9f36f37bmr3562323ejt.91.1702559421446; Thu, 14 Dec 2023 05:10:21 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id vq2-20020a170907a4c200b00a22faee6649sm2547776ejc.117.2023.12.14.05.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 05:10:21 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Abel Vesa Subject: [PATCH 1/4] arm64: dts: qcom: x1e80100: add ADSP audio codec macros Date: Thu, 14 Dec 2023 14:10:13 +0100 Message-Id: <20231214131016.30502-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> References: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8650. The nodes are exactly the same as on SM8550 and SM8650. Cc: Abel Vesa Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 85 ++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 8c18d7f82166..8bc6e544bbc9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2981,6 +2981,91 @@ nsp_noc: interconnect@320c0000 { #interconnect-cells =3D <2>; }; =20 + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-= macro"; + reg =3D <0 0x06aa0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE= _COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + sound-name-prefix =3D "WSA2"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-ma= cro"; + reg =3D <0 0x06ac0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-ma= cro"; + reg =3D <0 0x06ae0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-= macro"; + reg =3D <0 0x06b00000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + sound-name-prefix =3D "WSA"; + }; + + lpass_vamacro: codec@6d44000 { + compatible =3D "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-ma= cro"; + reg =3D <0 0x06d44000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", + "macro", + "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + lpass_tlmm: pinctrl@6e80000 { compatible =3D "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lp= i-pinctrl"; reg =3D <0 0x06e80000 0 0x20000>, --=20 2.34.1 From nobody Sat Dec 27 22:54:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B47AC4332F for ; Thu, 14 Dec 2023 13:10:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573255AbjLNNKX (ORCPT ); Thu, 14 Dec 2023 08:10:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573217AbjLNNKU (ORCPT ); Thu, 14 Dec 2023 08:10:20 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B03CD123 for ; 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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id vq2-20020a170907a4c200b00a22faee6649sm2547776ejc.117.2023.12.14.05.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 05:10:22 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Abel Vesa Subject: [PATCH 2/4] arm64: dts: qcom: x1e80100: add Soundwire controllers Date: Thu, 14 Dec 2023 14:10:14 +0100 Message-Id: <20231214131016.30502-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> References: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes for LPASS Soundwire v2.0.0 controllers. Difference against SM8550: 1. Update port configs to match reference implementation, 2. LPASS TLMM GPIO14 is not used as WCD_SR_TX_DATA2 pin but as GPIO (camera). Cc: Abel Vesa Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 226 +++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 8bc6e544bbc9..262ff4700194 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2999,6 +2999,36 @@ lpass_wsa2macro: codec@6aa0000 { sound-name-prefix =3D "WSA2"; }; =20 + swr3: soundwire@6ab0000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ab0000 0 0x10000>; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + interrupts =3D ; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8= 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_rxmacro: codec@6ac0000 { compatible =3D "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-ma= cro"; reg =3D <0 0x06ac0000 0 0x1000>; @@ -3016,6 +3046,36 @@ lpass_rxmacro: codec@6ac0000 { #sound-dai-cells =3D <1>; }; =20 + swr1: soundwire@6ad0000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ad0000 0 0x10000>; + clocks =3D <&lpass_rxmacro>; + clock-names =3D "iface"; + interrupts =3D ; + label =3D "RX"; + + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; + + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_txmacro: codec@6ae0000 { compatible =3D "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-ma= cro"; reg =3D <0 0x06ae0000 0 0x1000>; @@ -3051,6 +3111,68 @@ lpass_wsamacro: codec@6b00000 { sound-name-prefix =3D "WSA"; }; =20 + swr0: soundwire@6b10000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06b10000 0 0x10000>; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + interrupts =3D ; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8= 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + swr2: soundwire@6d30000 { + compatible =3D "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06d30000 0 0x10000>; + clocks =3D <&lpass_txmacro>; + clock-names =3D "iface"; + interrupts =3D , + ; + interrupt-names =3D "core", "wakeup"; + label =3D "TX"; + + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <1>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + lpass_vamacro: codec@6d44000 { compatible =3D "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-ma= cro"; reg =3D <0 0x06d44000 0 0x1000>; @@ -3078,6 +3200,110 @@ lpass_tlmm: pinctrl@6e80000 { gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; }; =20 lpass_ag_noc: interconnect@7e40000 { --=20 2.34.1 From nobody Sat Dec 27 22:54:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5174CC4332F for ; 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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id vq2-20020a170907a4c200b00a22faee6649sm2547776ejc.117.2023.12.14.05.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 05:10:23 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Abel Vesa Subject: [PATCH 3/4] arm64: dts: qcom: x1e80100-crd: add WCD9385 Audio Codec Date: Thu, 14 Dec 2023 14:10:15 +0100 Message-Id: <20231214131016.30502-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> References: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX and TX. Cc: Abel Vesa Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-crd.dts index 4f7f83d49847..aa5c4199bd2c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -18,6 +18,32 @@ aliases { serial0 =3D &uart21; }; =20 + audio-codec { + compatible =3D "qcom,wcd9385-codec"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wcd_default>; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_l15b_1p8>; + vdd-rxtx-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob1>; + + #sound-dai-cells =3D <1>; + }; + chosen { stdout-path =3D "serial0:115200n8"; }; @@ -607,6 +633,28 @@ &remoteproc_cdsp { status =3D "okay"; }; =20 +&swr1 { + status =3D "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; +}; + +&swr2 { + status =3D "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + qcom,tx-port-mapping =3D <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -649,6 +697,14 @@ reset-n-pins { drive-strength =3D <16>; }; }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio191"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; }; =20 &uart21 { --=20 2.34.1 From nobody Sat Dec 27 22:54:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD9EEC4332F for ; Thu, 14 Dec 2023 13:10:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573289AbjLNNKd (ORCPT ); Thu, 14 Dec 2023 08:10:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573249AbjLNNKV (ORCPT ); Thu, 14 Dec 2023 08:10:21 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88D5098 for ; Thu, 14 Dec 2023 05:10:27 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-50dfac6c0beso6245687e87.2 for ; Thu, 14 Dec 2023 05:10:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702559425; x=1703164225; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zv75S7w86iylwPFGSxZB3llZQ1CBvgYvd4ByAnD/noo=; b=ooozgHBCLPG7b5uiAjlgreD4y/TbzVDVOKHh6n2gOPqt9yoiLZxSU0GIm80wcrnpfN v785ozc2D54bEgNo4Ad3sBsqjQ3EW/GnbVau6U5WwWTXOseky6e+vAqW26HVMxnJDTHi RN6HZ534+trJnwlOIq1MKKc3hCpX4zSo6AwPb8d7LFh3RsQYDn37MRONFemyf1ngeFrp L7+Z4O4t3MvKjpu+kRLJ3od+1oGOwxapTwIabu61wfhdbC57pOFtjTGP6fFRg8eTSYXr fq85FADEuKH5fQbhigx+qUFS7CsgAD1ILNfzv/2sb6tqIuvwP37P/tG8Jhu3ZUxU+0HV l+cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702559425; x=1703164225; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zv75S7w86iylwPFGSxZB3llZQ1CBvgYvd4ByAnD/noo=; b=Ghz/i8LEybHINwpt63lJJMfFDog8eu1L3Hq5CKndU0RBCVqR1w75ZoegIhS7VCM1Uy 36Il4PXJO7n4hA91jPNCqJJQYlG6KC8003bHJZrakBV9MBlcym/9AP6XuUpiX/pSzc01 D2HLSYFvi9uzliSuzkGo7BAhjTOO7pOfIF9p+DMjzu1mZJMqNqwoM7PCwUo5erM0yyVs 2HbdZkUKwxXBqRZ1QIAZTu8zNPqbMlfmkbiB5qC42LpdD8rFUXv6G151pgmT/zHj6PCJ NhoJDOIGZNcIsKKh7D+ibzsmVsbTv/VTb7Ckv43FCu36yqEfUUAUPZZKcRjFikKo8xoF zv3Q== X-Gm-Message-State: AOJu0YyAghEl+Kio8/442sSZhWf1pr2isFjeAi9a2thlYgY00vbzR99t WdMPOjX69NgFdUXxOZBaYICsZA== X-Google-Smtp-Source: AGHT+IF0vB1K8s/4fuVHqhai7UgCQdRmqfPqB9YHWPZoeT+Mr22NJijQycQ9o1jR1Qugup8i4kwm9A== X-Received: by 2002:a19:5211:0:b0:50d:1679:5a50 with SMTP id m17-20020a195211000000b0050d16795a50mr4560724lfb.40.1702559425766; Thu, 14 Dec 2023 05:10:25 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id vq2-20020a170907a4c200b00a22faee6649sm2547776ejc.117.2023.12.14.05.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 05:10:25 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Abel Vesa Subject: [PATCH 4/4] arm64: dts: qcom: x1e80100-crd: add WSA8845 speakers Date: Thu, 14 Dec 2023 14:10:16 +0100 Message-Id: <20231214131016.30502-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> References: <20231214131016.30502-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes for four WSA8845 speakers. Unlike previous boards like SM8550-QRD, this board has four speakers spread over two Soundwire buses instead of two speakers on one bus. Each pair of speakers shares the reset GPIO thus pinctrl property is only in one of them. Cc: Abel Vesa Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 76 +++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-crd.dts index aa5c4199bd2c..8b4e5577048a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -543,6 +543,24 @@ touchscreen@10 { }; }; =20 +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + &mdss { status =3D "okay"; }; @@ -633,6 +651,35 @@ &remoteproc_cdsp { status =3D "okay"; }; =20 +&swr0 { + status =3D "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + pinctrl-0 =3D <&spkr_01_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "WooferLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + /* pinctrl in left_woofer node because of sharing the GPIO*/ + powerdown-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TwitterLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; +}; + &swr1 { status =3D "okay"; =20 @@ -655,6 +702,35 @@ wcd_tx: codec@0,3 { }; }; =20 +&swr3 { + status =3D "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + pinctrl-0 =3D <&spkr_23_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "WooferRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + /* pinctrl in right_woofer node because of sharing the GPIO*/ + powerdown-gpios =3D <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TwitterRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ --=20 2.34.1