From nobody Sun Dec 28 03:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B4F1C4332F for ; Thu, 14 Dec 2023 09:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235648AbjLNJL1 (ORCPT ); Thu, 14 Dec 2023 04:11:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229693AbjLNJLY (ORCPT ); Thu, 14 Dec 2023 04:11:24 -0500 Received: from mail-oo1-xc2d.google.com (mail-oo1-xc2d.google.com [IPv6:2607:f8b0:4864:20::c2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A9CFA6 for ; Thu, 14 Dec 2023 01:11:30 -0800 (PST) Received: by mail-oo1-xc2d.google.com with SMTP id 006d021491bc7-5907ded6287so4874650eaf.0 for ; Thu, 14 Dec 2023 01:11:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702545090; x=1703149890; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qSz/bHjwwlCoYKLoGELFqaslJ84OPxmUtiMSGQ7rw5w=; b=XTQLYjWNdgcQ8/lXSmRA0ZBBTxyxE3gbpqWTGG/vXpNQkxpAUdS8Hoe/gdiTm3r9VI nTs64WOBZ5J993BlJlWlZPxdZe7DX7PhkqLRd8VH7LDUpbvAs4e9nh/2oq+PBY4qNbCN 2FoCXCeKuuuxaVu71HAH/WFCp3KKO7bSs8tBjfosDlxvb15Fnc7cTSqUIsLZKKIwAoze JkQtKFiA2fyhFCmSDfe1hIOJoOHR8NCnbcXuTWrm4WN1Petx+dDQJ686JJSj/yJcwYSH bwtFm7nMoMt+XlUE4WF6utBb9XC2DhquNd3JVplCMzUR36qON6xrtmBj7r+raRG3SSUm gM4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702545090; x=1703149890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qSz/bHjwwlCoYKLoGELFqaslJ84OPxmUtiMSGQ7rw5w=; b=MjBR1bZ6tAWJaDJgydkrcaOhmEuhI5ET5x+eoIkIAfg8VOCdLAlJT7h0xUgiDy+8Ia SJA3MKHFbSuU7iLftC5mtnSImwmuLqFwbP/W9ArPg0UQf6ZjI/Ho0njqyrMRVA80z56c WhG+Xx4aFCYqrvCaRxz4RJyMRjAF1MntvSzYiuJ175LHAM6TmOOJtS7DIUi5rFffTgKn r5LEAqxZVzjYZ7S6of0T/5NTiLwvXBY8KksVedXwAKLAFEJazGBMKGf/INx3V70GTOyc EHOOHAiPgC+ON69LwTX+jGSbBagx9gwSZ8tWjLWsdkgT/U6GMva02MJUP3H+uYTBX4u5 rH0A== X-Gm-Message-State: AOJu0YzxZrWxYepP8lJ870lNwCDtMJK5mE1DD7z6Ma6cgdVGNCI30tjY uH7SnzHloKqJus8qZ7F4IftA X-Google-Smtp-Source: AGHT+IFUVL6JpWZGgVnmUsFb1wbwEnnw9CziVP9PAhqAu89DLKiGvOjnVwYt+11NDZPhiMjBcQeYqQ== X-Received: by 2002:a05:6358:7504:b0:172:962c:cb2c with SMTP id k4-20020a056358750400b00172962ccb2cmr1593062rwg.14.1702545089664; Thu, 14 Dec 2023 01:11:29 -0800 (PST) Received: from localhost.localdomain ([117.213.102.12]) by smtp.gmail.com with ESMTPSA id qt13-20020a05620a8a0d00b0077d75164ef9sm5144119qkn.124.2023.12.14.01.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 01:11:29 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 02/16] phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API Date: Thu, 14 Dec 2023 14:40:47 +0530 Message-Id: <20231214091101.45713-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231214091101.45713-1-manivannan.sadhasivam@linaro.org> References: <20231214091101.45713-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Device drivers should just rely on the clocks provided by the devicetree and enable/disable them based on the requirement. There is no need to validate the clocks provided by devicetree in the driver. That's the job of DT schema. So let's switch to devm_clk_bulk_get_all() API that just gets the clocks provided by devicetree and remove hardcoded clocks info. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 61 +++---------------------- 1 file changed, 7 insertions(+), 54 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 514fa14df634..174b105fda82 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -837,9 +837,6 @@ struct qmp_phy_cfg { /* Additional sequence for HS G4 */ const struct qmp_phy_cfg_tbls tbls_hs_g4; =20 - /* clock ids to be requested */ - const char * const *clk_list; - int num_clks; /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -865,6 +862,7 @@ struct qmp_ufs { void __iomem *rx2; =20 struct clk_bulk_data *clks; + int num_clks; struct regulator_bulk_data *vregs; struct reset_control *ufs_reset; =20 @@ -897,20 +895,6 @@ static inline void qphy_clrbits(void __iomem *base, u3= 2 offset, u32 val) readl(base + offset); } =20 -/* list of clocks required by phy */ -static const char * const msm8996_ufs_phy_clk_l[] =3D { - "ref", -}; - -/* the primary usb3 phy on sm8250 doesn't have a ref clock */ -static const char * const sm8450_ufs_phy_clk_l[] =3D { - "qref", "ref", "ref_aux", -}; - -static const char * const sdm845_ufs_phy_clk_l[] =3D { - "ref", "ref_aux", -}; - /* list of regulators */ static const char * const qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", @@ -948,9 +932,6 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), }, =20 - .clk_list =3D msm8996_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), - .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -986,8 +967,6 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sm8450_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1020,8 +999,6 @@ static const struct qmp_phy_cfg sc7280_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), }, - .clk_list =3D sm8450_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v4_regs_layout, @@ -1054,8 +1031,6 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1080,8 +1055,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { .serdes =3D sdm845_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v3_regs_layout, @@ -1108,8 +1081,6 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { .serdes =3D sm6115_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v2_regs_layout, @@ -1136,8 +1107,6 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg =3D= { .serdes =3D sdm845_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v3_regs_layout, @@ -1172,8 +1141,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { .pcs =3D sm8150_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v4_regs_layout, @@ -1206,8 +1173,6 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D= { .pcs =3D sm8150_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v4_regs_layout, @@ -1240,8 +1205,6 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1274,8 +1237,6 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D= { .pcs =3D sm8350_ufsphy_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), }, - .clk_list =3D sm8450_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v5_regs_layout, @@ -1296,8 +1257,6 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg =3D= { .pcs =3D sm8550_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8550_ufsphy_pcs), }, - .clk_list =3D sdm845_ufs_phy_clk_l, - .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D ufsphy_v6_regs_layout, @@ -1383,7 +1342,7 @@ static int qmp_ufs_com_init(struct qmp_ufs *qmp) return ret; } =20 - ret =3D clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + ret =3D clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); if (ret) goto err_disable_regulators; =20 @@ -1403,7 +1362,7 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) =20 reset_control_assert(qmp->ufs_reset); =20 - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -1573,19 +1532,13 @@ static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) =20 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; struct device *dev =3D qmp->dev; - int num =3D cfg->num_clks; - int i; =20 - qmp->clks =3D devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); - if (!qmp->clks) - return -ENOMEM; + qmp->num_clks =3D devm_clk_bulk_get_all(dev, &qmp->clks); + if (qmp->num_clks < 0) + return qmp->num_clks; =20 - for (i =3D 0; i < num; i++) - qmp->clks[i].id =3D cfg->clk_list[i]; - - return devm_clk_bulk_get(dev, num, qmp->clks); + return 0; } =20 static void qmp_ufs_clk_release_provider(void *res) --=20 2.25.1