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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a1cbe52300csm9026226ejc.56.2023.12.14.00.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 00:25:12 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Andrzej Hajda , Daniel Vetter , David Airlie , Inki Dae , Jagan Teki , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Marek Szyprowski , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v8 1/3] drm: bridge: samsung-dsim: enter display mode in the enable() callback Date: Thu, 14 Dec 2023 09:24:04 +0100 Message-ID: <20231214082457.18737-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> References: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The synaptics-r63353 (panel-bridge) can only be configured in command mode. So, samsung-dsim (bridge) must not be in display mode during the prepare()/unprepare() of the panel-bridge. Setting the "pre_enable_prev_first" flag to true allows the prepare() of the panel-bridge to be called between the pre_enabled() and enabled() of the bridge. So, the bridge can enter display mode only in the enabled(). The unprepare() of the panel-bridge is instead called between the disable() and post_disable() of the bridge. So, the disable() must exit the display mode (i .e. enter command mode) to allow the panel-bridge to receive DSI commands. samsung_dsim_atomic_pre_enable -> command mode r63353_panel_prepare -> send DSI commands samsung_dsim_atomic_enable -> enter display mode samsung_dsim_atomic_disable -> exit display mode (command mode) r63353_panel_unprepare -> send DSI commands samsung_dsim_atomic_post_disable Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/gpu/drm/bridge/samsung-dsim.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index be5914caa17d..15bf05b2bbe4 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1494,7 +1494,6 @@ static void samsung_dsim_atomic_pre_enable(struct drm= _bridge *bridge, return; =20 samsung_dsim_set_display_mode(dsi); - samsung_dsim_set_display_enable(dsi, true); } } =20 @@ -1507,6 +1506,7 @@ static void samsung_dsim_atomic_enable(struct drm_bri= dge *bridge, samsung_dsim_set_display_mode(dsi); samsung_dsim_set_display_enable(dsi, true); } else { + samsung_dsim_set_display_enable(dsi, true); samsung_dsim_set_stop_state(dsi, false); } =20 @@ -1524,6 +1524,8 @@ static void samsung_dsim_atomic_disable(struct drm_br= idge *bridge, if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) samsung_dsim_set_stop_state(dsi, true); =20 + samsung_dsim_set_display_enable(dsi, false); + dsi->state &=3D ~DSIM_STATE_VIDOUT_AVAILABLE; } =20 @@ -1532,7 +1534,8 @@ static void samsung_dsim_atomic_post_disable(struct d= rm_bridge *bridge, { struct samsung_dsim *dsi =3D bridge_to_dsi(bridge); =20 - samsung_dsim_set_display_enable(dsi, false); + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + samsung_dsim_set_stop_state(dsi, true); =20 dsi->state &=3D ~DSIM_STATE_ENABLED; pm_runtime_put_sync(dsi->dev); --=20 2.43.0 From nobody Sun Dec 28 00:47:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 836C2C4332F for ; Thu, 14 Dec 2023 08:25:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234474AbjLNIZP (ORCPT ); Thu, 14 Dec 2023 03:25:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234379AbjLNIZJ (ORCPT ); Thu, 14 Dec 2023 03:25:09 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20E77CF for ; Thu, 14 Dec 2023 00:25:16 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-a1e2ded3d9fso940818766b.0 for ; Thu, 14 Dec 2023 00:25:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1702542314; x=1703147114; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LRuU/Yf3+WOs2/s3BqHchrpBnPmBNhkaR5Vfu/UBGmU=; b=Vxnoh+LR7PQWwgamSvAokbYu3vryfTezhkvquOV6U28OlfG1L6wb/nzKzgvySxmy+m GOjg+hctnIzyCBUe0gOgKQHJXxZi46NCehuEeffC4/svjahd9e2fCEjksjC2JzmM++CU NJuUBXHKKvJ7HUKK/F9UO97L4MODttUtlIIF8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702542314; x=1703147114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LRuU/Yf3+WOs2/s3BqHchrpBnPmBNhkaR5Vfu/UBGmU=; b=LeKDBGpGKtXoTV2/xe9pXVQrxYjAwObsAFh7dYUX8uOA0FEbznLWwDiHiJig09DcM1 591H6/eDspBxomSOOoE224m6SI18cEIFvTWxg/9yiPlSF8APU2kd3QNtPVsswYj9PvVx DQiNy3nK777nN7vRn70n+GTfqtzO1LiBmUcpAY6mAxLs74jE6/slRa86c3QcJ+IPhTNp /EG3zK9yxbhwcCfl25DZtOBe9/DbPCyXGqoZ46dASiphrOaJdq2tfrg6cdWGjMmS5dGp eOn8zTirZr1EXMEmJ899bKvF9vnTGjLDhe9q+v+8Y5RpzBRa/xAe5gl/dVmSPosFt7PZ M7dA== X-Gm-Message-State: AOJu0YySafNfhHWkBZ+Qy4PvUB4vUrHZVCZ9uYo6Y2vvEsAGwqf8QPVz fYdbaQteCCOzvvABN2w1/TY0DoRFAdHK4eg/u7yHAg== X-Google-Smtp-Source: AGHT+IGZX6MZKKB2rJE3wqGAwfl1WteX/NIbcyKkXwIIBFqD2w9vCPZFUXPnyXVLFk4gqxuEac1EfQ== X-Received: by 2002:a17:907:86a6:b0:a17:3097:3f6e with SMTP id qa38-20020a17090786a600b00a1730973f6emr6566930ejc.30.1702542314396; Thu, 14 Dec 2023 00:25:14 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-182-13-188.retail.telecomitalia.it. [80.182.13.188]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a1cbe52300csm9026226ejc.56.2023.12.14.00.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 00:25:14 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Andrzej Hajda , Daniel Vetter , David Airlie , Inki Dae , Jagan Teki , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Marek Szyprowski , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v8 2/3] drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting Date: Thu, 14 Dec 2023 09:24:05 +0100 Message-ID: <20231214082457.18737-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> References: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The patch completes the setting of CLKLANE_STOP for the imx8mn and imx8mp platforms (i. e. not exynos). Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/gpu/drm/bridge/samsung-dsim.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 15bf05b2bbe4..13f181c99d7e 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -96,6 +96,7 @@ #define DSIM_MFLUSH_VS BIT(29) /* This flag is valid only for exynos3250/3472/5260/5430 */ #define DSIM_CLKLANE_STOP BIT(30) +#define DSIM_NON_CONTINUOUS_CLKLANE BIT(31) =20 /* DSIM_ESCMODE */ #define DSIM_TX_TRIGGER_RST BIT(4) @@ -945,8 +946,12 @@ static int samsung_dsim_init_link(struct samsung_dsim = *dsi) * power consumption. */ if (driver_data->has_clklane_stop && - dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + reg |=3D DSIM_NON_CONTINUOUS_CLKLANE; + reg |=3D DSIM_CLKLANE_STOP; + } samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); =20 lanes_mask =3D BIT(dsi->lanes) - 1; --=20 2.43.0 From nobody Sun Dec 28 00:47:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2068DC4167D for ; Thu, 14 Dec 2023 08:25:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234533AbjLNIZR (ORCPT ); Thu, 14 Dec 2023 03:25:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234398AbjLNIZM (ORCPT ); Thu, 14 Dec 2023 03:25:12 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 663CBCF for ; Thu, 14 Dec 2023 00:25:17 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-54cb4fa667bso10835338a12.3 for ; Thu, 14 Dec 2023 00:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1702542315; x=1703147115; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P9aQAquZ5xS5RyqBzg0IY2qUUlWniNS/41pwDJpEejQ=; b=NFqUpxjKCxOsZo+iE+xAxX9NY7ONSBStE2fQdOaxytfmborWT/dYel5xc1TNh7co9l K+dsMlTA+cGnceOQWY0+zR8gHlGiQXoCwQsmd3Ovgojk6lTJSac2izwjBfv7/D5Pouk2 4lIFiPXmpJ7Anr7Ba5D81Zko6gDmUlUvWeG+I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702542315; x=1703147115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P9aQAquZ5xS5RyqBzg0IY2qUUlWniNS/41pwDJpEejQ=; b=AbyBhD28o6SHhBZeScX3oGTvjAs6gmFxiHSrG8pfLrlSApCe24L3q8QKFWV0E96ywJ BZOab/I69XPk4rRg0CCxQ0osyirLzGF5SOYdD5pnOchGoISFZQB/1HT28egkUiBqCSP/ KPWdrMDluhr/A5FOhU0jkMYa3FJJRN8593KUEng1CYFpi8hnv37IcHYRSxbILk2oda9I 1O34/YdLHpnX/KFswZtw+gnLZj5URrffAYjHgqLqev1Li+sqOC5FJXVmUqToCgNNYLcu EyoSrI1fEfDuqU9xsBI1jJWCh+O1bdlt8aHpjGotuxiXA2m0wbUi92rFHri/Wkj36BLA iQfg== X-Gm-Message-State: AOJu0YyMDP2AA+TzC61euE4IEj3NLhgejXrMqL/rzHO24rakQ1z5xPXx BOOTqaLt+yatG4YgkxuEYBOfvUmlXRSdGrk/4q4Fow== X-Google-Smtp-Source: AGHT+IGXmb2qWB6+qNi8bEZzQAr8bB7d/GG7MzQ1wC+nf012IA2Tojo2jjKmrxUTmAMjbBuurmiIBQ== X-Received: by 2002:a17:906:154:b0:a22:fb34:dab5 with SMTP id 20-20020a170906015400b00a22fb34dab5mr995470ejh.67.1702542315601; Thu, 14 Dec 2023 00:25:15 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-182-13-188.retail.telecomitalia.it. [80.182.13.188]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a1cbe52300csm9026226ejc.56.2023.12.14.00.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 00:25:15 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 3/3] arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup Date: Thu, 14 Dec 2023 09:24:06 +0100 Message-ID: <20231214082457.18737-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> References: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Trimarchi Add the display and nodes required for its operation. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- Changes in v8: - Move the 'status' property to the end of the list of nodes: - pwm1 - lcdif - mipi_dsi - Add a newline between properties and child node (mipi_dsi_out). - Sort the iomuxc node alphabetically - Rename pwm1grp to blgrp Changes in v7: - Drop [3/4] dt-bindings: display: panel: Add synaptics r63353 panel contro= ller because applied. Changes in v6: - Drop patches: - [06/10] drm/panel: Add Synaptics R63353 panel driver - [07/10] dt-bindings: display: panel: Add Ilitek ili9805 panel controller - [08/10] drm/panel: Add Ilitek ILI9805 panel driver - [09/10] drm/panel: ilitek-ili9805: add support for Tianma TM041XDHG01 p= anel Because applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (= drm-misc-next) Drop patches: - [01/10] drm/bridge: Fix bridge disable logic - [02/10] drm/bridge: Fix a use case in the bridge disable logic Because they are wrong Changes in v3: - Replace "synaptics,r63353" compatible with "syna,r63353", as required by vendor-prefixes.yaml. - Squash patch [09/11] dt-bindings: ili9805: add compatible string for Tian= ma TM041XDHG01 into [07/11] dt-bindings: display: panel: Add Ilitek ili9805 panel contro= ller. Changes in v2: - Adjust the mipi_dsi node based on the latest patches merged into the mainline in the dtsi files it includes. - Added to the series the following patches: - 0001 drm/bridge: Fix bridge disable logic - 0002 drm/bridge: Fix a use case in the bridge disable logic - 0003 samsung-dsim: enter display mode in the enable() callback - 0004 drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting .../freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 + .../freescale/imx8mn-bsh-smm-s2-display.dtsi | 121 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display= .dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/= arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index 22a754d438f1..bbb07c650da9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; =20 #include "imx8mn.dtsi" +#include "imx8mn-bsh-smm-s2-display.dtsi" =20 / { chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b= /arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi new file mode 100644 index 000000000000..7675583a6b67 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 BSH + */ + +/ { + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm1 0 700000 0>; /* 700000 ns =3D 1337Hz */ + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <50>; + status =3D "okay"; + }; + + reg_3v3_dvdd: regulator-3v3-O3 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dvdd>; + regulator-name =3D "3v3-dvdd-supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_v3v3_avdd: regulator-3v3-O2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_avdd>; + regulator-name =3D "3v3-avdd-supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio1 5 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_bl>; + status =3D "okay"; +}; + +&lcdif { + assigned-clocks =3D <&clk IMX8MN_VIDEO_PLL1>; + assigned-clock-rates =3D <594000000>; + status =3D "okay"; +}; + +&pgc_dispmix { + assigned-clocks =3D <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB= >; + assigned-clock-parents =3D <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS= _PLL1_800M>; + assigned-clock-rates =3D <500000000>, <200000000>; +}; + +&mipi_dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + samsung,esc-clock-frequency =3D <20000000>; + samsung,pll-clock-frequency =3D <12000000>; + status =3D "okay"; + + panel@0 { + compatible =3D "sharp,ls068b3sx02", "syna,r63353"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel>; + reg =3D <0>; + + backlight =3D <&backlight>; + dvdd-supply =3D <®_3v3_dvdd>; + avdd-supply =3D <®_v3v3_avdd>; + reset-gpios =3D <&gpio4 29 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mipi_dsi_out>; + }; + }; + + }; + + ports { + port@1 { + reg =3D <1>; + + mipi_dsi_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; + +&gpu { + status =3D "okay"; +}; + +&iomuxc { + pinctrl_avdd: avddgrp { + fsl,pins =3D < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */ + >; + }; + + /* This is for both PWM and voltage regulators for display */ + pinctrl_bl: blgrp { + fsl,pins =3D < + MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16 + >; + }; + + pinctrl_dvdd: dvddgrp { + fsl,pins =3D < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */ + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */ + >; + }; +}; --=20 2.43.0