From nobody Fri Sep 20 08:26:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB65CC10F13 for ; Thu, 14 Dec 2023 06:00:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235351AbjLNGAH (ORCPT ); Thu, 14 Dec 2023 01:00:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235409AbjLNF7q (ORCPT ); Thu, 14 Dec 2023 00:59:46 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 009A919AE; Wed, 13 Dec 2023 21:58:54 -0800 (PST) X-UUID: da1827989a4511eea5db2bebc7c28f94-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=o+uFOxS7n5grSNHrAFSx8XCQRvD6lGHMhzCBfr8ABok=; b=HQei70YyMsCagpVWBBq+9XOlgy7sf2MXe7+oqmZkCfUDaTk1X4JZL1gX6LDuBmgquRaDeavYBXYSbCSLumeiNh0siIc5tyIufEojckSrQfsnRZNyeGlDjqB6Hhz6rGOdReVpucoMVCBy1IF34U+wVxQWAg5PK3ghYUlRZardJAM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:a4f865f1-1354-440c-a352-6b0b32c5d865,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:b8fc2e61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: da1827989a4511eea5db2bebc7c28f94-20231214 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 371681131; Thu, 14 Dec 2023 13:58:49 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:49 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 09/23] soc: mediatek: Support reset bit mapping in mmsys driver Date: Thu, 14 Dec 2023 13:58:33 +0800 Message-ID: <20231214055847.4936-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ drivers/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 1b160fcc1d27..fee958d0b8a6 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct reset_control= ler_dev *rcdev, unsigned l u32 offset; u32 reg; =20 + if (mmsys->data->rst_tb) { + if (id >=3D mmsys->data->num_resets) { + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=3D%u)\n", + id, mmsys->data->num_resets); + return -EINVAL; + } + id =3D mmsys->data->rst_tb[id]; + } + offset =3D (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); id =3D id % MMSYS_SW_RESET_PER_REG; reg =3D mmsys->data->sw0_rst_offset + offset; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index 9d8507f98b7a..d370192737ca 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,6 +78,8 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 =20 +#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u8 *rst_tb; const u32 num_resets; const bool is_vppsys; const u8 vsync_len; --=20 2.18.0