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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rajendra Nayak Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-alpha-pll.c | 26 ++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 05898d2a8b22..85f8e2ad0b37 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -52,6 +52,7 @@ #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U= 1]) +#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U= 2]) #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U= 1]) @@ -228,6 +229,21 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [PLL_OFF_ALPHA_VAL] =3D 0x24, [PLL_OFF_ALPHA_VAL_U] =3D 0x28, }, + [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] =3D { + [PLL_OFF_L_VAL] =3D 0x04, + [PLL_OFF_ALPHA_VAL] =3D 0x08, + [PLL_OFF_USER_CTL] =3D 0x0c, + [PLL_OFF_USER_CTL_U] =3D 0x10, + [PLL_OFF_CONFIG_CTL] =3D 0x14, + [PLL_OFF_CONFIG_CTL_U] =3D 0x18, + [PLL_OFF_CONFIG_CTL_U1] =3D 0x1c, + [PLL_OFF_CONFIG_CTL_U2] =3D 0x20, + [PLL_OFF_TEST_CTL] =3D 0x24, + [PLL_OFF_TEST_CTL_U] =3D 0x28, + [PLL_OFF_TEST_CTL_U1] =3D 0x2c, + [PLL_OFF_OPMODE] =3D 0x30, + [PLL_OFF_STATUS] =3D 0x3c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); =20 @@ -2093,6 +2109,16 @@ const struct clk_ops clk_alpha_pll_zonda_ops =3D { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); =20 +const struct clk_ops clk_alpha_pll_zonda_ole_ops =3D { + .enable =3D clk_zonda_pll_enable, + .disable =3D clk_zonda_pll_disable, + .is_enabled =3D clk_trion_pll_is_enabled, + .recalc_rate =3D clk_trion_pll_recalc_rate, + .round_rate =3D clk_alpha_pll_round_rate, + .set_rate =3D clk_zonda_pll_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_zonda_ole_ops); + void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap = *regmap, const struct alpha_pll_config *config) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index a1a75bb12fe8..99a3db9de4a1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -21,6 +21,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID =3D CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, + CLK_ALPHA_PLL_TYPE_ZONDA_OLE, CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, @@ -42,6 +43,7 @@ enum { PLL_OFF_CONFIG_CTL, PLL_OFF_CONFIG_CTL_U, PLL_OFF_CONFIG_CTL_U1, + PLL_OFF_CONFIG_CTL_U2, PLL_OFF_TEST_CTL, PLL_OFF_TEST_CTL_U, PLL_OFF_TEST_CTL_U1, @@ -119,6 +121,7 @@ struct alpha_pll_config { u32 config_ctl_val; u32 config_ctl_hi_val; u32 config_ctl_hi1_val; + u32 config_ctl_hi2_val; u32 user_ctl_val; u32 user_ctl_hi_val; u32 user_ctl_hi1_val; @@ -173,6 +176,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid= _5lpe_ops; =20 extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops +extern const struct clk_ops clk_alpha_pll_zonda_ole_ops; =20 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; --=20 2.34.1