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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id n11-20020a0565120acb00b0050be6038170sm1928838lfu.48.2023.12.14.10.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 10:13:52 -0800 (PST) From: Konrad Dybcio Date: Thu, 14 Dec 2023 19:13:40 +0100 Subject: [PATCH 3/6] arm64: dts: qcom: sc8180x: Add missing MDP clocks MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231214-topic-sc8180_fixes-v1-3-421904863006@linaro.org> References: <20231214-topic-sc8180_fixes-v1-0-421904863006@linaro.org> In-Reply-To: <20231214-topic-sc8180_fixes-v1-0-421904863006@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Maximilian Luz , Gustave Monce , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ROT clock is required for the MDP block to function (looks like some others depend on it), and whike the LUT clock's purpose is not clear, it's likely better to turn on all of MDP's dependencies rather than not doing so. Add these clocks under the MDP node. This also makes Primus work without clk_ignore_unused (as far as the dmesg-visible errors go, anyway). Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 09b4e66367bf..c970dfb11fe5 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2702,11 +2702,15 @@ mdss_mdp: mdp@ae01000 { clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names =3D "iface", "bus", "core", - "vsync"; + "vsync", + "rot", + "lut"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; --=20 2.40.1