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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id br7-20020a056512400700b0050bfe37d28asm1641026lfb.34.2023.12.13.08.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 08:29:07 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 3/4] arm64: dts: qcom: sm8550: move Soundwire pinctrl to its nodes Date: Wed, 13 Dec 2023 17:28:55 +0100 Message-Id: <20231213162856.188566-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213162856.188566-1-krzysztof.kozlowski@linaro.org> References: <20231213162856.188566-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Pin configuration for Soundwire bus should be set in Soundwire controller nodes, not in the associated macro codec node. This placement change should not have big impact in general, because macro codec is a clock provider for Soundwire controller, thus its devices is probed first. However it will have impact for disabled Soundwire buses, e.g. WSA2, because after this change the pins will be left in default state. We also follow similar approach in newer SoCs, like Qualcomm SM8650. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 1f06fd33d1ce..d8f79b5895f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2050,8 +2050,6 @@ lpass_wsa2macro: codec@6aa0000 { =20 #clock-cells =3D <0>; clock-output-names =3D "wsa2-mclk"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&wsa2_swr_active>; #sound-dai-cells =3D <1>; }; =20 @@ -2063,6 +2061,9 @@ swr3: soundwire-controller@6ab0000 { clock-names =3D "iface"; label =3D "WSA2"; =20 + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + qcom,din-ports =3D <4>; qcom,dout-ports =3D <9>; =20 @@ -2096,8 +2097,6 @@ lpass_rxmacro: codec@6ac0000 { =20 #clock-cells =3D <0>; clock-output-names =3D "mclk"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&rx_swr_active>; #sound-dai-cells =3D <1>; }; =20 @@ -2109,6 +2108,9 @@ swr1: soundwire-controller@6ad0000 { clock-names =3D "iface"; label =3D "RX"; =20 + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + qcom,din-ports =3D <1>; qcom,dout-ports =3D <11>; =20 @@ -2142,8 +2144,6 @@ lpass_txmacro: codec@6ae0000 { =20 #clock-cells =3D <0>; clock-output-names =3D "mclk"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tx_swr_active>; #sound-dai-cells =3D <1>; }; =20 @@ -2161,8 +2161,6 @@ lpass_wsamacro: codec@6b00000 { =20 #clock-cells =3D <0>; clock-output-names =3D "mclk"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&wsa_swr_active>; #sound-dai-cells =3D <1>; }; =20 @@ -2174,6 +2172,9 @@ swr0: soundwire-controller@6b10000 { clock-names =3D "iface"; label =3D "WSA"; =20 + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + qcom,din-ports =3D <4>; qcom,dout-ports =3D <9>; =20 @@ -2203,6 +2204,9 @@ swr2: soundwire-controller@6d30000 { clock-names =3D "iface"; label =3D "TX"; =20 + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + qcom,din-ports =3D <4>; qcom,dout-ports =3D <0>; qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; --=20 2.34.1