From nobody Fri Dec 19 01:00:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C406C4332F for ; Wed, 13 Dec 2023 08:02:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378734AbjLMICa (ORCPT ); Wed, 13 Dec 2023 03:02:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232673AbjLMIC3 (ORCPT ); Wed, 13 Dec 2023 03:02:29 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DA2CD0; Wed, 13 Dec 2023 00:02:35 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3BD82M9m002149; Wed, 13 Dec 2023 02:02:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1702454542; bh=MBKsgsuYGX4k9jFCM4rlwljZIghlRoJN70MfqBeb5vE=; h=From:To:CC:Subject:Date; b=YUK5ZNUqD6b2dti6512xGmw2HQ7IJkClY5Wpyzd6r6lQOaooZYgLPkoh7wEfrHFca 50RiyyjvAfQWnpbBrpF0leDLnRLpPfzfym7a/Y1Auhyf8Q7ZltCNNFpVjI1oUilbnO Ob7bVL6A1/dulOtTp/8ms1hHKnAKelGWWiB4G90A= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3BD82MmU126291 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Dec 2023 02:02:22 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 13 Dec 2023 02:02:21 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 13 Dec 2023 02:02:21 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3BD82HU8024879; Wed, 13 Dec 2023 02:02:18 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , , , Subject: [PATCH v2] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupts for ICSSG2 Date: Wed, 13 Dec 2023 13:32:16 +0530 Message-ID: <20231213080216.1710730-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable interrupt mode of operation of the DP83867 Ethernet PHY which is used by ICSSG2. The DP83867 PHY driver already supports interrupt handling for interrupts generated by the PHY. Thus, add the necessary device-tree support to enable it. Since the GPIO1_87 line is muxed with EXT_REFCLK1 and SYNC1_OUT, update the pinmux to select GPIO1_87 for routing the interrupt. As the same interrupt line and therefore the same pinmux configuration is applicable to both Ethernet PHYs used by ICSSG2, allocate the pinmux resource to the first Ethernet PHY alone. Signed-off-by: Siddharth Vadapalli Reviewed-by: MD Danish Anwar --- Hello, This patch is based on linux-next tagged next-20231213. v1: https://lore.kernel.org/r/20231120063159.539306-1-s-vadapalli@ti.com/ Changes since v1: - Rebased patch on next-20231213. - Collected Reviewed-by tag from MD Danish Anwar - Moved pinctrl from MDIO node to Ethernet PHY node based on feedback from Nishanth Menon - Replaced the hard-coded value 0x2 with IRQ_TYPE_EDGE_FALLING for setting the interrupt trigger type and level flag based on feedback from Nishanth Menon - Included dt-bindings/interrupt-controller/irq.h in the overlay. - Updated commit message with details of the pinmux resource allocation. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/= dts/ti/k3-am654-icssg2.dtso index ec8cf20ca3ac..6eabdfa0d602 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso @@ -8,6 +8,7 @@ /dts-v1/; /plugin/; =20 +#include #include #include "k3-pinctrl.h" =20 @@ -124,6 +125,15 @@ AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_= GPO4.PRG2_RGMII1_RX_CTL */ }; }; =20 +&main_pmx1 { + /* Select GPIO1_87 for ICSSG2 PHY interrupt */ + icssg2_phy_irq_pins_default: icssg2-phy-irq-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0014, PIN_INPUT, 7) /* (A22) EXT_REFCLK1.GPIO1_87 */ + >; + }; +}; + &icssg2_mdio { status =3D "okay"; pinctrl-names =3D "default"; @@ -132,13 +142,20 @@ &icssg2_mdio { #size-cells =3D <0>; =20 icssg2_phy0: ethernet-phy@0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg2_phy_irq_pins_default>; + reg =3D <0>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <87 IRQ_TYPE_EDGE_FALLING>; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; }; =20 icssg2_phy1: ethernet-phy@3 { reg =3D <3>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <87 IRQ_TYPE_EDGE_FALLING>; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; }; --=20 2.34.1