From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37020C4332F for ; Wed, 13 Dec 2023 07:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378677AbjLMHGK (ORCPT ); Wed, 13 Dec 2023 02:06:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235321AbjLMHFa (ORCPT ); Wed, 13 Dec 2023 02:05:30 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EB1412B; Tue, 12 Dec 2023 23:05:16 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73Chb032127; Wed, 13 Dec 2023 15:03:12 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:08 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 01/16] riscv: errata: Rename defines for Andes Date: Wed, 13 Dec 2023 15:02:46 +0800 Message-ID: <20231213070301.1684751-2-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73Chb032127 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use "ANDES" rather than "ANDESTECH" to unify the naming convention with directory, file names, Kconfig options and other definitions. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- Changes v1 -> v2: - No change Changes v2 -> v3: - Rewrite commit message (suggested by Conor) Changes v3 -> v4: - Include Conor's Acked-by tag Changes v4 -> v5: - Include Prabhakar's RB tag --- arch/riscv/errata/andes/errata.c | 10 +++++----- arch/riscv/include/asm/errata_list.h | 4 ++-- arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/err= ata.c index 17a904869724..f2708a9494a1 100644 --- a/arch/riscv/errata/andes/errata.c +++ b/arch/riscv/errata/andes/errata.c @@ -18,9 +18,9 @@ #include #include =20 -#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL -#define ANDESTECH_AX45MP_MIMPID 0x500UL -#define ANDESTECH_SBI_EXT_ANDES 0x0900031E +#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDES_AX45MP_MIMPID 0x500UL +#define ANDES_SBI_EXT_ANDES 0x0900031E =20 #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 =20 @@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void) * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing= and * cache is controllable only then CMO will be applied to the platform. */ - ret =3D sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROU= ND, + ret =3D sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, 0, 0, 0, 0, 0, 0); =20 return ret.error ? 0 : ret.value; @@ -50,7 +50,7 @@ static void errata_probe_iocp(unsigned int stage, unsigne= d long arch_id, unsigne =20 done =3D true; =20 - if (arch_id !=3D ANDESTECH_AX45MP_MARCHID || impid !=3D ANDESTECH_AX45MP_= MIMPID) + if (arch_id !=3D ANDES_AX45MP_MARCHID || impid !=3D ANDES_AX45MP_MIMPID) return; =20 if (!ax45mp_iocp_sw_workaround()) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 83ed25e43553..4ed21a62158c 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -12,8 +12,8 @@ #include =20 #ifdef CONFIG_ERRATA_ANDES -#define ERRATA_ANDESTECH_NO_IOCP 0 -#define ERRATA_ANDESTECH_NUMBER 1 +#define ERRATA_ANDES_NO_IOCP 0 +#define ERRATA_ANDES_NUMBER 1 #endif =20 #ifdef CONFIG_ERRATA_SIFIVE diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index e55407ace0c3..2f2bb0c84f9a 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -5,7 +5,7 @@ #ifndef ASM_VENDOR_LIST_H #define ASM_VENDOR_LIST_H =20 -#define ANDESTECH_VENDOR_ID 0x31e +#define ANDES_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 =20 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 319a1da0358b..0128b161bfda 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactur= er_info_t *cpu_mfr_info =20 switch (cpu_mfr_info->vendor_id) { #ifdef CONFIG_ERRATA_ANDES - case ANDESTECH_VENDOR_ID: + case ANDES_VENDOR_ID: cpu_mfr_info->patch_func =3D andes_errata_patch_func; break; #endif --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19EAEC4332F for ; Wed, 13 Dec 2023 07:05:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378648AbjLMHFF (ORCPT ); Wed, 13 Dec 2023 02:05:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233173AbjLMHE6 (ORCPT ); Wed, 13 Dec 2023 02:04:58 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E423D3; Tue, 12 Dec 2023 23:05:02 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73HrQ032167; Wed, 13 Dec 2023 15:03:17 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:13 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Date: Wed, 13 Dec 2023 15:02:47 +0800 Message-ID: <20231213070301.1684751-3-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73HrQ032167 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, the implementation of the RISC-V INTC driver uses the interrupt cause as hardware interrupt number and has a limitation of supporting a maximum of 64 interrupts. However, according to the privileged spec, interrupt causes >=3D 16 are defined for platform use. This limitation prevents to fully utilize the available local interrupt sources. Additionally, the interrupt number used on RISC-V are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf or T-Head's PMU interrupt) being currently used for supervisor mode. Switch to using irq_domain_create_tree() to create the radix tree map, so a larger number of hardware interrupts can be handled. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang --- Changes v1 -> v2: - Fixed irq mapping failure checking (suggested by Cl=C3=A9ment and Anup) Changes v2 -> v3: - No change Changes v3 -> v4: (Suggested by Thomas [1]) - Use pr_warn_ratelimited instead - Fix coding style and commit message Changes v4 -> v5: (Suggested by Thomas) - Fix commit message [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2= 663486-3-peterlin@andestech.com/#25573085 --- drivers/irqchip/irq-riscv-intc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index e8d01b14ccdd..2fdd40f2a791 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -24,10 +24,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) { unsigned long cause =3D regs->cause & ~CAUSE_IRQ_FLAG; =20 - if (unlikely(cause >=3D BITS_PER_LONG)) - panic("unexpected interrupt cause"); - - generic_handle_domain_irq(intc_domain, cause); + if (generic_handle_domain_irq(intc_domain, cause)) + pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", + cause); } =20 /* @@ -117,8 +116,7 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) { int rc; =20 - intc_domain =3D irq_domain_create_linear(fn, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + intc_domain =3D irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); - return 0; } =20 --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 206E1C4332F for ; Wed, 13 Dec 2023 07:05:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378532AbjLMHE7 (ORCPT ); Wed, 13 Dec 2023 02:04:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233100AbjLMHE5 (ORCPT ); Wed, 13 Dec 2023 02:04:57 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87CE0AD; Tue, 12 Dec 2023 23:05:02 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73MKo032193; Wed, 13 Dec 2023 15:03:22 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:18 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Date: Wed, 13 Dec 2023 15:02:48 +0800 Message-ID: <20231213070301.1684751-4-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73MKo032193 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the Andes hart-level interrupt controller. This controller provides interrupt mask/unmask functions to access the custom register (SLIE) where the non-standard S-mode local interrupt enable bits are located. To share the riscv_intc_domain_map() with the generic RISC-V INTC and ACPI, add a chip parameter to riscv_intc_init_common(), so it can be passed to the irq_domain_set_info() as private data. Andes hart-level interrupt controller requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node. e.g., cpu0: cpu@0 { compatible =3D "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells =3D <0x01>; compatible =3D "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC Changes v3 -> v4: (Suggested by Thomas [1]) - Add comment to andes irq chip function - Refine code flow to share with generic RISC-V INTC and ACPI - Move Andes specific definitions to include/linux/soc/andes/irq.h Changes v4 -> v5: (Suggested by Thomas) - Fix commit message - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of m= ask - Do not set chip_data to the chip itself with irq_domain_set_info() - Follow reverse fir tree order variable declarations [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3= 657156-1-peterlin@andestech.com/ --- drivers/irqchip/irq-riscv-intc.c | 53 ++++++++++++++++++++++++++++---- include/linux/soc/andes/irq.h | 17 ++++++++++ 2 files changed, 64 insertions(+), 6 deletions(-) create mode 100644 include/linux/soc/andes/irq.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 2fdd40f2a791..0b6bf3fb1dba 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; =20 @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } =20 +static void andes_intc_irq_mask(struct irq_data *d) +{ + /* + * Andes specific S-mode local interrupt causes (hwirq) + * are defined as (256 + n) and controlled by n-th bit + * of SLIE. + */ + unsigned int mask =3D BIT(d->hwirq - ANDES_SLI_CAUSE_BASE); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask =3D BIT(d->hwirq - ANDES_SLI_CAUSE_BASE); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -69,11 +95,20 @@ static struct irq_chip riscv_intc_chip =3D { .irq_eoi =3D riscv_intc_irq_eoi, }; =20 +static struct irq_chip andes_intc_chip =3D { + .name =3D "RISC-V INTC", + .irq_mask =3D andes_intc_irq_mask, + .irq_unmask =3D andes_intc_irq_unmask, + .irq_eoi =3D riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct irq_chip *chip =3D d->host_data; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, + irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, NULL, NULL); =20 return 0; @@ -112,11 +147,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } =20 -static int __init riscv_intc_init_common(struct fwnode_handle *fn) +static int __init riscv_intc_init_common(struct fwnode_handle *fn, + struct irq_chip *chip) { int rc; =20 - intc_domain =3D irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); + intc_domain =3D irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -136,8 +172,9 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc; + struct irq_chip *chip =3D &riscv_intc_chip; unsigned long hartid; + int rc; =20 rc =3D riscv_of_parent_hartid(node, &hartid); if (rc < 0) { @@ -162,10 +199,14 @@ static int __init riscv_intc_init(struct device_node = *node, return 0; } =20 - return riscv_intc_init_common(of_node_to_fwnode(node)); + if (of_device_is_compatible(node, "andestech,cpu-intc")) + chip =3D &andes_intc_chip; + + return riscv_intc_init_common(of_node_to_fwnode(node), chip); } =20 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); =20 #ifdef CONFIG_ACPI =20 @@ -192,7 +233,7 @@ static int __init riscv_intc_acpi_init(union acpi_subta= ble_headers *header, return -ENOMEM; } =20 - return riscv_intc_init_common(fn); + return riscv_intc_init_common(fn, &riscv_intc_chip); } =20 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h new file mode 100644 index 000000000000..f03e68fea261 --- /dev/null +++ b/include/linux/soc/andes/irq.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __ANDES_IRQ_H +#define __ANDES_IRQ_H + +/* Andes PMU irq number */ +#define ANDES_RV_IRQ_PMU 18 +#define ANDES_SLI_CAUSE_BASE 256 + +/* Andes PMU related registers */ +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 +#define ANDES_CSR_SCOUNTEROF 0x9d4 + +#endif /* __ANDES_IRQ_H */ --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78F72C4332F for ; Wed, 13 Dec 2023 07:06:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378764AbjLMHGU (ORCPT ); Wed, 13 Dec 2023 02:06:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378661AbjLMHFi (ORCPT ); Wed, 13 Dec 2023 02:05:38 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A346D5D; Tue, 12 Dec 2023 23:05:29 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73RVh032220; Wed, 13 Dec 2023 15:03:27 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:23 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Date: Wed, 13 Dec 2023 15:02:49 +0800 Message-ID: <20231213070301.1684751-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73RVh032220 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add "andestech,cpu-intc" compatible string to indicate that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - Add const entry instead of enum (Suggested by Conor) Changes v4 -> v5: - Include Conor's Acked-by - Include Prabhakar's Reviewed-by --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index f392e367d673..50307554478f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -100,7 +100,11 @@ properties: const: 1 =20 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc =20 interrupt-controller: true =20 --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2085AC4167B for ; Wed, 13 Dec 2023 07:05:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378553AbjLMHFB (ORCPT ); Wed, 13 Dec 2023 02:05:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233168AbjLMHE6 (ORCPT ); Wed, 13 Dec 2023 02:04:58 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E2C5BD; Tue, 12 Dec 2023 23:05:02 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73Wlc032242; Wed, 13 Dec 2023 15:03:32 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:28 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Date: Wed, 13 Dec 2023 15:02:50 +0800 Message-ID: <20231213070301.1684751-6-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73Wlc032242 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - No change Changes v4 -> v5: - Include Geert's Reviewed-by - Include Prabhakar's Reviewed/Tested-by --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/= dts/renesas/r9a07g043f.dtsi index eb301d8eb2b0..78072e80793d 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -38,7 +38,7 @@ cpu0: cpu@0 { =20 cpu0_intc: interrupt-controller { #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; + compatible =3D "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5BCAC4332F for ; Wed, 13 Dec 2023 07:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378732AbjLMHFl (ORCPT ); Wed, 13 Dec 2023 02:05:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235320AbjLMHFa (ORCPT ); Wed, 13 Dec 2023 02:05:30 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A09012A; Tue, 12 Dec 2023 23:05:16 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73buI032263; Wed, 13 Dec 2023 15:03:37 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:33 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Date: Wed, 13 Dec 2023 15:02:51 +0800 Message-ID: <20231213070301.1684751-7-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73buI032263 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The interrupt enable/disable operations are already performed by the IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during enable_percpu_irq()/disable_percpu_irq(). It can be done only once. Signed-off-by: Yu Chien Peter Lin --- This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE} in the initial PATCH3 [1]. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1= 002738-4-peterlin@andestech.com/ Changes v1 -> v2: - New patch Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - No change --- drivers/perf/riscv_pmu_sbi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..2edbc37abadf 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struc= t hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq =3D riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); - csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } =20 @@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct h= list_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); - csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); } =20 /* Disable all counters access for user mode now */ --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED2A6C4332F for ; Wed, 13 Dec 2023 07:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378530AbjLMHFP (ORCPT ); Wed, 13 Dec 2023 02:05:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378524AbjLMHE7 (ORCPT ); Wed, 13 Dec 2023 02:04:59 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6B64E3; Tue, 12 Dec 2023 23:05:04 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73giG032285; Wed, 13 Dec 2023 15:03:42 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:38 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Date: Wed, 13 Dec 2023 15:02:52 +0800 Message-ID: <20231213070301.1684751-8-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73giG032285 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The custom PMU extension aims to support perf event sampling prior to the ratification of Sscofpmf. Instead of diverting the bits and register reserved for future standard, a set of custom registers is added. Hence, we may consider it as a CPU feature rather than an erratum. T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU for proper functioning as of this commit. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren Reviewed-by: Conor Dooley --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs() Changes v3 -> v4: - No change Changes v4 -> v5: - Include Guo's Reviewed-by - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD --- arch/riscv/Kconfig.errata | 13 ------------- arch/riscv/errata/thead/errata.c | 19 ------------------- arch/riscv/include/asm/errata_list.h | 15 +-------------- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + drivers/perf/Kconfig | 13 +++++++++++++ drivers/perf/riscv_pmu_sbi.c | 19 ++++++++++++++----- 7 files changed, 30 insertions(+), 51 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..0d19f47d1018 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO =20 If you don't know what to do here, say "Y". =20 -config ERRATA_THEAD_PMU - bool "Apply T-Head PMU errata" - depends on ERRATA_THEAD && RISCV_PMU_SBI - default y - help - The T-Head C9xx cores implement a PMU overflow extension very - similar to the core SSCOFPMF extension. - - This will apply the overflow errata to handle the non-standard - behaviour via the regular SBI PMU driver and interface. - - If you don't know what to do here, say "Y". - endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index 0554ed4bf087..5de5f7209132 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage, return true; } =20 -static bool errata_probe_pmu(unsigned int stage, - unsigned long arch_id, unsigned long impid) -{ - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU)) - return false; - - /* target-c9xx cores report arch_id and impid as 0 */ - if (arch_id !=3D 0 || impid !=3D 0) - return false; - - if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - return true; -} - static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage, if (errata_probe_cmo(stage, archid, impid)) cpu_req_errata |=3D BIT(ERRATA_THEAD_CMO); =20 - if (errata_probe_pmu(stage, archid, impid)) - cpu_req_errata |=3D BIT(ERRATA_THEAD_PMU); - return cpu_req_errata; } =20 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 4ed21a62158c..9bccc2ba0eb5 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -25,8 +25,7 @@ #ifdef CONFIG_ERRATA_THEAD #define ERRATA_THEAD_PBMT 0 #define ERRATA_THEAD_CMO 1 -#define ERRATA_THEAD_PMU 2 -#define ERRATA_THEAD_NUMBER 3 +#define ERRATA_THEAD_NUMBER 2 #endif =20 #ifdef __ASSEMBLY__ @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2( \ "r"((unsigned long)(_start) + (_size)) \ : "a0") =20 -#define THEAD_C9XX_RV_IRQ_PMU 17 -#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 - -#define ALT_SBI_PMU_OVERFLOW(__ovl) \ -asm volatile(ALTERNATIVE( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ - "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ - THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ - CONFIG_ERRATA_THEAD_PMU) \ - : "=3Dr" (__ovl) : \ - : "memory") - #endif /* __ASSEMBLY__ */ =20 #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 06d30526ef3b..c85ee34c78d9 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -57,6 +57,7 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 +#define RISCV_ISA_EXT_XTHEADPMU 45 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b3785ffc1570..e606f588d366 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -185,6 +185,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU), }; =20 const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 273d67ecf6d2..6cef15ec7c25 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -86,6 +86,19 @@ config RISCV_PMU_SBI full perf feature support i.e. counter overflow, privilege mode filtering, counter configuration. =20 +config THEAD_CUSTOM_PMU + bool "T-Head custom PMU support" + depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI + default y + help + The T-Head C9xx cores implement a PMU overflow extension very + similar to the core SSCOFPMF extension. + + This will patch the overflow CSR and handle the non-standard + behaviour via the regular SBI PMU driver and interface. + + If you don't know what to do here, say "Y". + config ARM_PMU_ACPI depends on ARM_PMU && ACPI def_bool y diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 2edbc37abadf..31ca79846399 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -20,10 +20,21 @@ #include #include =20 -#include #include #include =20 +#define THEAD_C9XX_RV_IRQ_PMU 17 +#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 + +#define ALT_SBI_PMU_OVERFLOW(__ovl) \ +asm volatile(ALTERNATIVE( \ + "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ + 0, RISCV_ISA_EXT_XTHEADPMU, \ + CONFIG_THEAD_CUSTOM_PMU) \ + : "=3Dr" (__ovl) : \ + : "memory") + #define SYSCTL_NO_USER_ACCESS 0 #define SYSCTL_USER_ACCESS 1 #define SYSCTL_LEGACY 2 @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, s= truct platform_device *pde if (riscv_isa_extension_available(NULL, SSCOFPMF)) { riscv_pmu_irq_num =3D RV_IRQ_PMU; riscv_pmu_use_irq =3D true; - } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) && - riscv_cached_mvendorid(0) =3D=3D THEAD_VENDOR_ID && - riscv_cached_marchid(0) =3D=3D 0 && - riscv_cached_mimpid(0) =3D=3D 0) { + } else if (riscv_isa_extension_available(NULL, XTHEADPMU) && + IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) { riscv_pmu_irq_num =3D THEAD_C9XX_RV_IRQ_PMU; riscv_pmu_use_irq =3D true; } --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85F0EC4167D for ; Wed, 13 Dec 2023 07:05:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378698AbjLMHFU (ORCPT ); Wed, 13 Dec 2023 02:05:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378554AbjLMHFC (ORCPT ); Wed, 13 Dec 2023 02:05:02 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63A0FAC; Tue, 12 Dec 2023 23:05:07 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73laq032307; Wed, 13 Dec 2023 15:03:47 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:43 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Date: Wed, 13 Dec 2023 15:02:53 +0800 Message-ID: <20231213070301.1684751-9-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73laq032307 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Andes PMU extension provides the same mechanism as Sscofpmf, allowing us to reuse the SBI PMU driver to support event sampling and mode filtering. To make use of this custom PMU extension, "xandespmu" needs to be appended to the riscv,isa-extensions for each cpu node in device-tree, and enable CONFIG_ANDES_CUSTOM_PMU. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang Co-developed-by: Locus Wei-Han Chen Signed-off-by: Locus Wei-Han Chen Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Reordered list in riscv_isa_ext[] - Removed mvendorid check in pmu_sbi_setup_irqs() Changes v3 -> v4: - No change Changes v4 -> v5: - Let ANDES_CUSTOM_PMU depend on ARCH_RENESAS - Include Prabhakar's Reviewed/Tested-by --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + drivers/perf/Kconfig | 14 ++++++++++++++ drivers/perf/riscv_pmu_sbi.c | 30 +++++++++++++++++++++++++----- 4 files changed, 41 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index c85ee34c78d9..cbfbc3505d2c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,6 +58,7 @@ #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 #define RISCV_ISA_EXT_XTHEADPMU 45 +#define RISCV_ISA_EXT_XANDESPMU 46 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e606f588d366..42fda134c4a3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -185,6 +185,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU), __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU), }; =20 diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 6cef15ec7c25..18f4c62eafc2 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -86,6 +86,20 @@ config RISCV_PMU_SBI full perf feature support i.e. counter overflow, privilege mode filtering, counter configuration. =20 +config ANDES_CUSTOM_PMU + bool "Andes custom PMU support" + depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI + default y + help + The Andes cores implement a PMU overflow extension very + similar to the core SSCOFPMF extension. + + This will patch the overflow/pending CSR and handle the + non-standard behaviour via the regular SBI PMU driver and + interface. + + If you don't know what to do here, say "Y". + config THEAD_CUSTOM_PMU bool "T-Head custom PMU support" depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 31ca79846399..1e0c709efbfc 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include #include @@ -27,14 +28,26 @@ #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 =20 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ -asm volatile(ALTERNATIVE( \ +asm volatile(ALTERNATIVE_2( \ "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ 0, RISCV_ISA_EXT_XTHEADPMU, \ - CONFIG_THEAD_CUSTOM_PMU) \ + CONFIG_THEAD_CUSTOM_PMU, \ + "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \ + 0, RISCV_ISA_EXT_XANDESPMU, \ + CONFIG_ANDES_CUSTOM_PMU) \ : "=3Dr" (__ovl) : \ : "memory") =20 +#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask) \ +asm volatile(ALTERNATIVE( \ + "csrc " __stringify(CSR_IP) ", %0\n\t", \ + "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \ + 0, RISCV_ISA_EXT_XANDESPMU, \ + CONFIG_ANDES_CUSTOM_PMU) \ + : : "r"(__irq_mask) \ + : "memory") + #define SYSCTL_NO_USER_ACCESS 0 #define SYSCTL_USER_ACCESS 1 #define SYSCTL_LEGACY 2 @@ -72,6 +85,7 @@ static int sysctl_perf_user_access __read_mostly =3D SYSC= TL_USER_ACCESS; static union sbi_pmu_ctr_info *pmu_ctr_list; static bool riscv_pmu_use_irq; static unsigned int riscv_pmu_irq_num; +static unsigned int riscv_pmu_irq_mask; static unsigned int riscv_pmu_irq; =20 /* Cache the available counters in a bitmask */ @@ -705,7 +719,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) =20 event =3D cpu_hw_evt->events[fidx]; if (!event) { - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); return IRQ_NONE; } =20 @@ -719,7 +733,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) * Overflow interrupt pending bit should only be cleared after stopping * all the counters to avoid any race condition. */ - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); =20 /* No overflow bit is set */ if (!overflow) @@ -791,7 +805,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struc= t hlist_node *node) =20 if (riscv_pmu_use_irq) { cpu_hw_evt->irq =3D riscv_pmu_irq; - csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } =20 @@ -823,8 +837,14 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, s= truct platform_device *pde IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) { riscv_pmu_irq_num =3D THEAD_C9XX_RV_IRQ_PMU; riscv_pmu_use_irq =3D true; + } else if (riscv_isa_extension_available(NULL, XANDESPMU) && + IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { + riscv_pmu_irq_num =3D ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU; + riscv_pmu_use_irq =3D true; } =20 + riscv_pmu_irq_mask =3D BIT(riscv_pmu_irq_num % BITS_PER_LONG); + if (!riscv_pmu_use_irq) return -EOPNOTSUPP; =20 --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C99FC4332F for ; Wed, 13 Dec 2023 07:06:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233256AbjLMHGG (ORCPT ); Wed, 13 Dec 2023 02:06:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235322AbjLMHFa (ORCPT ); Wed, 13 Dec 2023 02:05:30 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9D3C12D; Tue, 12 Dec 2023 23:05:16 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73rxS032328; Wed, 13 Dec 2023 15:03:53 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:49 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 09/16] dt-bindings: riscv: Add T-Head PMU extension description Date: Wed, 13 Dec 2023 15:02:54 +0800 Message-ID: <20231213070301.1684751-10-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73rxS032328 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the ISA string for T-Head performance monitor extension which provides counter overflow interrupt mechanism. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren Reviewed-by: Inochi Amaoto Acked-by: Conor Dooley --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change Changes v4 -> v5: - Include Guo's Reviewed-by - Include Inochi's Reviewed-by - Update to C910 documentation with its commit hash --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index c91ab0e46648..b5cb8ac7ac80 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -258,5 +258,11 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: xtheadpmu + description: + The T-Head performance monitor extension for counter overflow,= as ratified + in commit 4c4981 ("Initial commit") of Xuantie C910 user manua= l. + https://github.com/T-head-Semi/openc910/tree/main/doc + additionalProperties: true ... --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5754C4332F for ; Wed, 13 Dec 2023 07:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378729AbjLMHGQ (ORCPT ); Wed, 13 Dec 2023 02:06:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235268AbjLMHFe (ORCPT ); Wed, 13 Dec 2023 02:05:34 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4386213A; Tue, 12 Dec 2023 23:05:20 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD73wCq032352; Wed, 13 Dec 2023 15:03:58 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:54 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 10/16] dt-bindings: riscv: Add Andes PMU extension description Date: Wed, 13 Dec 2023 15:02:55 +0800 Message-ID: <20231213070301.1684751-11-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD73wCq032352 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the ISA string for Andes Technology performance monitor extension which provides counter overflow interrupt and mode filtering mechanisms. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- Changes v2 -> v3: - New patch Changes v3 -> v4: - Include Conor's Acked-by Changes v4 -> v5: - Include Prabhakar's Reviewed-by --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index b5cb8ac7ac80..daef6c3b1580 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -258,6 +258,13 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter= overflow + and privilege mode filtering. For more details, see Counter Re= lated + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf + - const: xtheadpmu description: The T-Head performance monitor extension for counter overflow,= as ratified --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEEFFC4332F for ; Wed, 13 Dec 2023 07:06:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378776AbjLMHG0 (ORCPT ); Wed, 13 Dec 2023 02:06:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378769AbjLMHFn (ORCPT ); Wed, 13 Dec 2023 02:05:43 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 221AB10F4; Tue, 12 Dec 2023 23:05:34 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD743Ru032519; Wed, 13 Dec 2023 15:04:03 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:59 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Date: Wed, 13 Dec 2023 15:02:56 +0800 Message-ID: <20231213070301.1684751-12-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD743Ru032519 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change Changes v4 -> v5: - Include Guo's Reviewed-by --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..7dcba86cfdd0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; #cooling-cells =3D <2>; =20 cpu0_intc: interrupt-controller { --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EFA0C4332F for ; Wed, 13 Dec 2023 07:06:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378770AbjLMHGX (ORCPT ); Wed, 13 Dec 2023 02:06:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378759AbjLMHFm (ORCPT ); Wed, 13 Dec 2023 02:05:42 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6549210F0; Tue, 12 Dec 2023 23:05:34 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD7488l032591; Wed, 13 Dec 2023 15:04:08 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:04:04 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Date: Wed, 13 Dec 2023 15:02:57 +0800 Message-ID: <20231213070301.1684751-13-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD7488l032591 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index aec6401a467b..8c0143f0a01b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -29,7 +29,7 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; =20 cpu0_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E656C4332F for ; Wed, 13 Dec 2023 07:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378726AbjLMHGm (ORCPT ); Wed, 13 Dec 2023 02:06:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378880AbjLMHFw (ORCPT ); Wed, 13 Dec 2023 02:05:52 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF93A183; Tue, 12 Dec 2023 23:05:48 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD74DLb032612; Wed, 13 Dec 2023 15:04:13 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:04:09 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Date: Wed, 13 Dec 2023 15:02:58 +0800 Message-ID: <20231213070301.1684751-14-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD74DLb032612 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++---------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..1d0b236f2e7a 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -260,7 +260,7 @@ cpu0: cpu@0 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <0>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -285,7 +285,7 @@ cpu1: cpu@1 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <1>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -310,7 +310,7 @@ cpu2: cpu@2 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <2>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -335,7 +335,7 @@ cpu3: cpu@3 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <3>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -360,7 +360,7 @@ cpu4: cpu@4 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <4>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -385,7 +385,7 @@ cpu5: cpu@5 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <5>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -410,7 +410,7 @@ cpu6: cpu@6 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <6>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -435,7 +435,7 @@ cpu7: cpu@7 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <7>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -460,7 +460,7 @@ cpu8: cpu@8 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <8>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -485,7 +485,7 @@ cpu9: cpu@9 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <9>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -510,7 +510,7 @@ cpu10: cpu@10 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <10>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -535,7 +535,7 @@ cpu11: cpu@11 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <11>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -560,7 +560,7 @@ cpu12: cpu@12 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <12>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -585,7 +585,7 @@ cpu13: cpu@13 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <13>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -610,7 +610,7 @@ cpu14: cpu@14 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <14>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -635,7 +635,7 @@ cpu15: cpu@15 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <15>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -660,7 +660,7 @@ cpu16: cpu@16 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <16>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -685,7 +685,7 @@ cpu17: cpu@17 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <17>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -710,7 +710,7 @@ cpu18: cpu@18 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <18>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -735,7 +735,7 @@ cpu19: cpu@19 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <19>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -760,7 +760,7 @@ cpu20: cpu@20 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <20>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -785,7 +785,7 @@ cpu21: cpu@21 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <21>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -810,7 +810,7 @@ cpu22: cpu@22 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <22>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -835,7 +835,7 @@ cpu23: cpu@23 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <23>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -860,7 +860,7 @@ cpu24: cpu@24 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <24>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -885,7 +885,7 @@ cpu25: cpu@25 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <25>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -910,7 +910,7 @@ cpu26: cpu@26 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <26>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -935,7 +935,7 @@ cpu27: cpu@27 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <27>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -960,7 +960,7 @@ cpu28: cpu@28 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <28>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -985,7 +985,7 @@ cpu29: cpu@29 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <29>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1010,7 +1010,7 @@ cpu30: cpu@30 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <30>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1035,7 +1035,7 @@ cpu31: cpu@31 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <31>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1060,7 +1060,7 @@ cpu32: cpu@32 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <32>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1085,7 +1085,7 @@ cpu33: cpu@33 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <33>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1110,7 +1110,7 @@ cpu34: cpu@34 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <34>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1135,7 +1135,7 @@ cpu35: cpu@35 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <35>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1160,7 +1160,7 @@ cpu36: cpu@36 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <36>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1185,7 +1185,7 @@ cpu37: cpu@37 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <37>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1210,7 +1210,7 @@ cpu38: cpu@38 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <38>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1235,7 +1235,7 @@ cpu39: cpu@39 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <39>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1260,7 +1260,7 @@ cpu40: cpu@40 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <40>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1285,7 +1285,7 @@ cpu41: cpu@41 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <41>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1310,7 +1310,7 @@ cpu42: cpu@42 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <42>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1335,7 +1335,7 @@ cpu43: cpu@43 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <43>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1360,7 +1360,7 @@ cpu44: cpu@44 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <44>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1385,7 +1385,7 @@ cpu45: cpu@45 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <45>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1410,7 +1410,7 @@ cpu46: cpu@46 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <46>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1435,7 +1435,7 @@ cpu47: cpu@47 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <47>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1460,7 +1460,7 @@ cpu48: cpu@48 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <48>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1485,7 +1485,7 @@ cpu49: cpu@49 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <49>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1510,7 +1510,7 @@ cpu50: cpu@50 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <50>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1535,7 +1535,7 @@ cpu51: cpu@51 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <51>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1560,7 +1560,7 @@ cpu52: cpu@52 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <52>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1585,7 +1585,7 @@ cpu53: cpu@53 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <53>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1610,7 +1610,7 @@ cpu54: cpu@54 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <54>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1635,7 +1635,7 @@ cpu55: cpu@55 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <55>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1660,7 +1660,7 @@ cpu56: cpu@56 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <56>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1685,7 +1685,7 @@ cpu57: cpu@57 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <57>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1710,7 +1710,7 @@ cpu58: cpu@58 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <58>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1735,7 +1735,7 @@ cpu59: cpu@59 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <59>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1760,7 +1760,7 @@ cpu60: cpu@60 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <60>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1785,7 +1785,7 @@ cpu61: cpu@61 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <61>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1810,7 +1810,7 @@ cpu62: cpu@62 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <62>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -1835,7 +1835,7 @@ cpu63: cpu@63 { riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg =3D <63>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E823C4332F for ; Wed, 13 Dec 2023 07:06:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378757AbjLMHGb (ORCPT ); Wed, 13 Dec 2023 02:06:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378863AbjLMHFv (ORCPT ); Wed, 13 Dec 2023 02:05:51 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEA2A13D; Tue, 12 Dec 2023 23:05:48 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD74IhD032637; Wed, 13 Dec 2023 15:04:18 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:04:14 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Date: Wed, 13 Dec 2023 15:02:59 +0800 Message-ID: <20231213070301.1684751-15-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD74IhD032637 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index ba4d2c673ac8..2dad2b22824a 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -22,7 +22,7 @@ c910_0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg =3D <0>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -46,7 +46,7 @@ c910_1: cpu@1 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg =3D <1>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -70,7 +70,7 @@ c910_2: cpu@2 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg =3D <2>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; @@ -94,7 +94,7 @@ c910_3: cpu@3 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg =3D <3>; i-cache-block-size =3D <64>; i-cache-size =3D <65536>; --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DE4DC4332F for ; Wed, 13 Dec 2023 07:06:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378861AbjLMHGq (ORCPT ); Wed, 13 Dec 2023 02:06:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378901AbjLMHFy (ORCPT ); Wed, 13 Dec 2023 02:05:54 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 050E71A6; Tue, 12 Dec 2023 23:05:52 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD74Nwb032659; Wed, 13 Dec 2023 15:04:23 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:04:20 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Date: Wed, 13 Dec 2023 15:03:00 +0800 Message-ID: <20231213070301.1684751-16-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD74Nwb032659 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xandespmu stands for Andes Performance Monitor Unit extension. Based on the added Andes PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Acked-by: Conor Dooley --- Changes v1 -> v2: - New patch Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - Include Geert's Reviewed-by - Include Prabhakar's Reviewed/Tested-by --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/= dts/renesas/r9a07g043f.dtsi index 78072e80793d..5f2f2181638a 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -26,7 +26,7 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xandespmu"; mmu-type =3D "riscv,sv39"; i-cache-size =3D <0x8000>; i-cache-line-size =3D <0x40>; --=20 2.34.1 From nobody Thu Dec 18 14:28:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F345C4332F for ; Wed, 13 Dec 2023 07:07:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378902AbjLMHG6 (ORCPT ); Wed, 13 Dec 2023 02:06:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378968AbjLMHGC (ORCPT ); Wed, 13 Dec 2023 02:06:02 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FDAF1AB; Tue, 12 Dec 2023 23:05:59 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD74Sii033205; Wed, 13 Dec 2023 15:04:28 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:04:24 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Date: Wed, 13 Dec 2023 15:03:01 +0800 Message-ID: <20231213070301.1684751-17-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BD74Sii033205 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Locus Wei-Han Chen Add the Andes AX45 JSON files that allows specifying symbolic event names for the raw PMU events. Signed-off-by: Locus Wei-Han Chen Reviewed-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang Tested-by: Lad Prabhakar --- Changes v1 -> v2: - No change Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - Include Prabhakar's Tested-by --- .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 5 files changed, 330 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.js= on create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instruction= s.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.j= son diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/to= ols/perf/pmu-events/arch/riscv/andes/ax45/firmware.json new file mode 100644 index 000000000000..9b4a032186a7 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json @@ -0,0 +1,68 @@ +[ + { + "ArchStdEvent": "FW_MISALIGNED_LOAD" + }, + { + "ArchStdEvent": "FW_MISALIGNED_STORE" + }, + { + "ArchStdEvent": "FW_ACCESS_LOAD" + }, + { + "ArchStdEvent": "FW_ACCESS_STORE" + }, + { + "ArchStdEvent": "FW_ILLEGAL_INSN" + }, + { + "ArchStdEvent": "FW_SET_TIMER" + }, + { + "ArchStdEvent": "FW_IPI_SENT" + }, + { + "ArchStdEvent": "FW_IPI_RECEIVED" + }, + { + "ArchStdEvent": "FW_FENCE_I_SENT" + }, + { + "ArchStdEvent": "FW_FENCE_I_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_SENT" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json = b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json new file mode 100644 index 000000000000..713a08c1a40f --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json @@ -0,0 +1,127 @@ +[ + { + "EventCode": "0x10", + "EventName": "cycle_count", + "BriefDescription": "Cycle count" + }, + { + "EventCode": "0x20", + "EventName": "inst_count", + "BriefDescription": "Retired instruction count" + }, + { + "EventCode": "0x30", + "EventName": "int_load_inst", + "BriefDescription": "Integer load instruction count" + }, + { + "EventCode": "0x40", + "EventName": "int_store_inst", + "BriefDescription": "Integer store instruction count" + }, + { + "EventCode": "0x50", + "EventName": "atomic_inst", + "BriefDescription": "Atomic instruction count" + }, + { + "EventCode": "0x60", + "EventName": "sys_inst", + "BriefDescription": "System instruction count" + }, + { + "EventCode": "0x70", + "EventName": "int_compute_inst", + "BriefDescription": "Integer computational instruction count" + }, + { + "EventCode": "0x80", + "EventName": "condition_br", + "BriefDescription": "Conditional branch instruction count" + }, + { + "EventCode": "0x90", + "EventName": "taken_condition_br", + "BriefDescription": "Taken conditional branch instruction count" + }, + { + "EventCode": "0xA0", + "EventName": "jal_inst", + "BriefDescription": "JAL instruction count" + }, + { + "EventCode": "0xB0", + "EventName": "jalr_inst", + "BriefDescription": "JALR instruction count" + }, + { + "EventCode": "0xC0", + "EventName": "ret_inst", + "BriefDescription": "Return instruction count" + }, + { + "EventCode": "0xD0", + "EventName": "control_trans_inst", + "BriefDescription": "Control transfer instruction count" + }, + { + "EventCode": "0xE0", + "EventName": "ex9_inst", + "BriefDescription": "EXEC.IT instruction count" + }, + { + "EventCode": "0xF0", + "EventName": "int_mul_inst", + "BriefDescription": "Integer multiplication instruction count" + }, + { + "EventCode": "0x100", + "EventName": "int_div_rem_inst", + "BriefDescription": "Integer division/remainder instruction count" + }, + { + "EventCode": "0x110", + "EventName": "float_load_inst", + "BriefDescription": "Floating-point load instruction count" + }, + { + "EventCode": "0x120", + "EventName": "float_store_inst", + "BriefDescription": "Floating-point store instruction count" + }, + { + "EventCode": "0x130", + "EventName": "float_add_sub_inst", + "BriefDescription": "Floating-point addition/subtraction instruction cou= nt" + }, + { + "EventCode": "0x140", + "EventName": "float_mul_inst", + "BriefDescription": "Floating-point multiplication instruction count" + }, + { + "EventCode": "0x150", + "EventName": "float_fused_muladd_inst", + "BriefDescription": "Floating-point fused multiply-add instruction count" + }, + { + "EventCode": "0x160", + "EventName": "float_div_sqrt_inst", + "BriefDescription": "Floating-point division or square-root instruction = count" + }, + { + "EventCode": "0x170", + "EventName": "other_float_inst", + "BriefDescription": "Other floating-point instruction count" + }, + { + "EventCode": "0x180", + "EventName": "int_mul_add_sub_inst", + "BriefDescription": "Integer multiplication and add/sub instruction coun= t" + }, + { + "EventCode": "0x190", + "EventName": "retired_ops", + "BriefDescription": "Retired operation count" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tool= s/perf/pmu-events/arch/riscv/andes/ax45/memory.json new file mode 100644 index 000000000000..c7401b526c77 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json @@ -0,0 +1,57 @@ +[ + { + "EventCode": "0x01", + "EventName": "ilm_access", + "BriefDescription": "ILM access" + }, + { + "EventCode": "0x11", + "EventName": "dlm_access", + "BriefDescription": "DLM access" + }, + { + "EventCode": "0x21", + "EventName": "icache_access", + "BriefDescription": "ICACHE access" + }, + { + "EventCode": "0x31", + "EventName": "icache_miss", + "BriefDescription": "ICACHE miss" + }, + { + "EventCode": "0x41", + "EventName": "dcache_access", + "BriefDescription": "DCACHE access" + }, + { + "EventCode": "0x51", + "EventName": "dcache_miss", + "BriefDescription": "DCACHE miss" + }, + { + "EventCode": "0x61", + "EventName": "dcache_load_access", + "BriefDescription": "DCACHE load access" + }, + { + "EventCode": "0x71", + "EventName": "dcache_load_miss", + "BriefDescription": "DCACHE load miss" + }, + { + "EventCode": "0x81", + "EventName": "dcache_store_access", + "BriefDescription": "DCACHE store access" + }, + { + "EventCode": "0x91", + "EventName": "dcache_store_miss", + "BriefDescription": "DCACHE store miss" + }, + { + "EventCode": "0xA1", + "EventName": "dcache_wb", + "BriefDescription": "DCACHE writeback" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json b/t= ools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json new file mode 100644 index 000000000000..a6d378cbaa74 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json @@ -0,0 +1,77 @@ +[ + { + "EventCode": "0xB1", + "EventName": "cycle_wait_icache_fill", + "BriefDescription": "Cycles waiting for ICACHE fill data" + }, + { + "EventCode": "0xC1", + "EventName": "cycle_wait_dcache_fill", + "BriefDescription": "Cycles waiting for DCACHE fill data" + }, + { + "EventCode": "0xD1", + "EventName": "uncached_ifetch_from_bus", + "BriefDescription": "Uncached ifetch data access from bus" + }, + { + "EventCode": "0xE1", + "EventName": "uncached_load_from_bus", + "BriefDescription": "Uncached load data access from bus" + }, + { + "EventCode": "0xF1", + "EventName": "cycle_wait_uncached_ifetch", + "BriefDescription": "Cycles waiting for uncached ifetch data from bus" + }, + { + "EventCode": "0x101", + "EventName": "cycle_wait_uncached_load", + "BriefDescription": "Cycles waiting for uncached load data from bus" + }, + { + "EventCode": "0x111", + "EventName": "main_itlb_access", + "BriefDescription": "Main ITLB access" + }, + { + "EventCode": "0x121", + "EventName": "main_itlb_miss", + "BriefDescription": "Main ITLB miss" + }, + { + "EventCode": "0x131", + "EventName": "main_dtlb_access", + "BriefDescription": "Main DTLB access" + }, + { + "EventCode": "0x141", + "EventName": "main_dtlb_miss", + "BriefDescription": "Main DTLB miss" + }, + { + "EventCode": "0x151", + "EventName": "cycle_wait_itlb_fill", + "BriefDescription": "Cycles waiting for Main ITLB fill data" + }, + { + "EventCode": "0x161", + "EventName": "pipe_stall_cycle_dtlb_miss", + "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss" + }, + { + "EventCode": "0x02", + "EventName": "mispredict_condition_br", + "BriefDescription": "Misprediction of conditional branches" + }, + { + "EventCode": "0x12", + "EventName": "mispredict_take_condition_br", + "BriefDescription": "Misprediction of taken conditional branches" + }, + { + "EventCode": "0x22", + "EventName": "mispredict_target_ret_inst", + "BriefDescription": "Misprediction of targets of Return instructions" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-= events/arch/riscv/mapfile.csv index c61b3d6ef616..5bf09af14c1b 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -15,3 +15,4 @@ # #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core +0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core --=20 2.34.1