From nobody Sun Dec 28 06:38:05 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62B84C4332F for ; Tue, 12 Dec 2023 20:48:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235213AbjLLUsP (ORCPT ); Tue, 12 Dec 2023 15:48:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235200AbjLLUrd (ORCPT ); Tue, 12 Dec 2023 15:47:33 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2284D5E for ; Tue, 12 Dec 2023 12:47:27 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-db7dd9a8bd6so6414593276.1 for ; Tue, 12 Dec 2023 12:47:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1702414046; x=1703018846; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=tGOeri4zVsC3MNu9Ed0LWydKBDXJJokVJF2VNK8BRVk=; b=X5V+vqdu4rRx6/QuFvsY47zBm84bIujdYZxTPW2AD0WHYgnfaRoVevpo6sWXEto0b6 oZwsZWzYb9gDrhgBzxu+THTwBLZ8fPyHHVvTE9ZlXJfg1tZQKOcqXdNtV+bpndAZwfC3 /MV7706/K+aUhBh/voz+HEVdgThbQHoEQb48hZZb4sOdhcuEDftYcKa2bZrSQv/ZqMuG X19/Yay/FHYKkR9RtdOgT+EbwF8+59Qbk23G5vF7gl56AwrxS5onaKhmv8JTV047UKsU yeljYe1hPWGWUiaf7o+EJ9K73crwYrNJKDGKPs37/03l4Ha15MEloY2ZSrX+FqrAQZuD zYfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702414046; x=1703018846; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tGOeri4zVsC3MNu9Ed0LWydKBDXJJokVJF2VNK8BRVk=; b=jmBdfJAObkKduPwtlzsYvS+wSw5Pa1QipW6S0E1tI6voHCbOTmWNzt8KzCHPZEUszG aPXopV8CyDWEYa1QXRv3VRgLl56qXbWG3gFv4qRi9O6bb46A6hrIa/iD5jYqBLKMKRar WchelxLRqsKlmAZevZvoHmJvzmAS98ZUPDuyMVnItN2ctHGkUh6dxU/2I3RUWhX3N2eZ T+oExyeAt4RWym6WC7sPVOpkGMJcynOkALxLuhCFd8Ca1FouVunAJkcBm6310ZED2Dou 3yv4rGUSmJHogolEML/4Iuiqc+BY82WRFMuZ+G0XWy5YdqscTFr6u6DxUNfoBKbqqGsA ZN0w== X-Gm-Message-State: AOJu0YwTj73B5uWi/JVm3h055S/QW3fHF6rTderf8QwjgH0DT1GNxW3r /+LocW7/TPHCSYoqV2O0PRiwrtACjw== X-Google-Smtp-Source: AGHT+IFppVJBjp9hY7iHinJP93UxPTzPiFhT3wxO7vIU807QdxxMvrP3Qy3oPO23G2jD8h0l1OPK9g9qng== X-Received: from sagi.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:241b]) (user=sagis job=sendgmr) by 2002:a25:8a09:0:b0:db5:4d59:3b30 with SMTP id g9-20020a258a09000000b00db54d593b30mr44477ybl.8.1702414046156; Tue, 12 Dec 2023 12:47:26 -0800 (PST) Date: Tue, 12 Dec 2023 12:46:30 -0800 In-Reply-To: <20231212204647.2170650-1-sagis@google.com> Mime-Version: 1.0 References: <20231212204647.2170650-1-sagis@google.com> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog Message-ID: <20231212204647.2170650-16-sagis@google.com> Subject: [RFC PATCH v5 15/29] KVM: selftests: TDX: Add TDX MSR read/write tests From: Sagi Shahar To: linux-kselftest@vger.kernel.org, Ackerley Tng , Ryan Afranji , Erdem Aktas , Sagi Shahar , Isaku Yamahata Cc: Sean Christopherson , Paolo Bonzini , Shuah Khan , Peter Gonda , Haibo Xu , Chao Peng , Vishal Annapurve , Roger Wang , Vipin Sharma , jmattson@google.com, dmatlack@google.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-mm@kvack.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The test verifies reads and writes for MSR registers with different access level. Signed-off-by: Sagi Shahar Signed-off-by: Ackerley Tng Signed-off-by: Ryan Afranji --- .../selftests/kvm/include/x86_64/tdx/tdx.h | 5 + .../selftests/kvm/lib/x86_64/tdx/tdx.c | 27 +++ .../selftests/kvm/x86_64/tdx_vm_tests.c | 209 ++++++++++++++++++ 3 files changed, 241 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h b/tools/t= esting/selftests/kvm/include/x86_64/tdx/tdx.h index 63788012bf94..85ba6aab79a7 100644 --- a/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h +++ b/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h @@ -9,11 +9,16 @@ #define TDG_VP_VMCALL_REPORT_FATAL_ERROR 0x10003 =20 #define TDG_VP_VMCALL_INSTRUCTION_IO 30 +#define TDG_VP_VMCALL_INSTRUCTION_RDMSR 31 +#define TDG_VP_VMCALL_INSTRUCTION_WRMSR 32 + void handle_userspace_tdg_vp_vmcall_exit(struct kvm_vcpu *vcpu); uint64_t tdg_vp_vmcall_instruction_io(uint64_t port, uint64_t size, uint64_t write, uint64_t *data); void tdg_vp_vmcall_report_fatal_error(uint64_t error_code, uint64_t data_g= pa); uint64_t tdg_vp_vmcall_get_td_vmcall_info(uint64_t *r11, uint64_t *r12, uint64_t *r13, uint64_t *r14); +uint64_t tdg_vp_vmcall_instruction_rdmsr(uint64_t index, uint64_t *ret_val= ue); +uint64_t tdg_vp_vmcall_instruction_wrmsr(uint64_t index, uint64_t value); =20 #endif // SELFTEST_TDX_TDX_H diff --git a/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c b/tools/testi= ng/selftests/kvm/lib/x86_64/tdx/tdx.c index e5a9e13c62e2..88ea6f2a6469 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c +++ b/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c @@ -87,3 +87,30 @@ uint64_t tdg_vp_vmcall_get_td_vmcall_info(uint64_t *r11,= uint64_t *r12, =20 return ret; } + +uint64_t tdg_vp_vmcall_instruction_rdmsr(uint64_t index, uint64_t *ret_val= ue) +{ + uint64_t ret; + struct tdx_hypercall_args args =3D { + .r11 =3D TDG_VP_VMCALL_INSTRUCTION_RDMSR, + .r12 =3D index, + }; + + ret =3D __tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT); + + if (ret_value) + *ret_value =3D args.r11; + + return ret; +} + +uint64_t tdg_vp_vmcall_instruction_wrmsr(uint64_t index, uint64_t value) +{ + struct tdx_hypercall_args args =3D { + .r11 =3D TDG_VP_VMCALL_INSTRUCTION_WRMSR, + .r12 =3D index, + .r13 =3D value, + }; + + return __tdx_hypercall(&args, 0); +} diff --git a/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c b/tools/test= ing/selftests/kvm/x86_64/tdx_vm_tests.c index 699cba36e9ce..5db3701cc6d9 100644 --- a/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c +++ b/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c @@ -515,6 +515,213 @@ void verify_guest_reads(void) printf("\t ... PASSED\n"); } =20 +/* + * Define a filter which denies all MSR access except the following: + * MSR_X2APIC_APIC_ICR: Allow read/write access (allowed by default) + * MSR_IA32_MISC_ENABLE: Allow read access + * MSR_IA32_POWER_CTL: Allow write access + */ +#define MSR_X2APIC_APIC_ICR 0x830 +static u64 tdx_msr_test_allow_bits =3D 0xFFFFFFFFFFFFFFFF; +struct kvm_msr_filter tdx_msr_test_filter =3D { + .flags =3D KVM_MSR_FILTER_DEFAULT_DENY, + .ranges =3D { + { + .flags =3D KVM_MSR_FILTER_READ, + .nmsrs =3D 1, + .base =3D MSR_IA32_MISC_ENABLE, + .bitmap =3D (uint8_t *)&tdx_msr_test_allow_bits, + }, { + .flags =3D KVM_MSR_FILTER_WRITE, + .nmsrs =3D 1, + .base =3D MSR_IA32_POWER_CTL, + .bitmap =3D (uint8_t *)&tdx_msr_test_allow_bits, + }, + }, +}; + +/* + * Verifies MSR read functionality. + */ +void guest_msr_read(void) +{ + uint64_t data; + uint64_t ret; + + ret =3D tdg_vp_vmcall_instruction_rdmsr(MSR_X2APIC_APIC_ICR, &data); + if (ret) + tdx_test_fatal(ret); + + ret =3D tdx_test_report_64bit_to_user_space(data); + if (ret) + tdx_test_fatal(ret); + + ret =3D tdg_vp_vmcall_instruction_rdmsr(MSR_IA32_MISC_ENABLE, &data); + if (ret) + tdx_test_fatal(ret); + + ret =3D tdx_test_report_64bit_to_user_space(data); + if (ret) + tdx_test_fatal(ret); + + /* We expect this call to fail since MSR_IA32_POWER_CTL is write only */ + ret =3D tdg_vp_vmcall_instruction_rdmsr(MSR_IA32_POWER_CTL, &data); + if (ret) { + ret =3D tdx_test_report_64bit_to_user_space(ret); + if (ret) + tdx_test_fatal(ret); + } else { + tdx_test_fatal(-99); + } + + tdx_test_success(); +} + +void verify_guest_msr_reads(void) +{ + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + + uint64_t data; + int ret; + + vm =3D td_create(); + td_initialize(vm, VM_MEM_SRC_ANONYMOUS, 0); + + /* + * Set explicit MSR filter map to control access to the MSR registers + * used in the test. + */ + printf("\t ... Setting test MSR filter\n"); + ret =3D kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR); + TEST_ASSERT(ret, "KVM_CAP_X86_USER_SPACE_MSR is unavailable"); + vm_enable_cap(vm, KVM_CAP_X86_USER_SPACE_MSR, KVM_MSR_EXIT_REASON_FILTER); + + ret =3D kvm_check_cap(KVM_CAP_X86_MSR_FILTER); + TEST_ASSERT(ret, "KVM_CAP_X86_MSR_FILTER is unavailable"); + + ret =3D ioctl(vm->fd, KVM_X86_SET_MSR_FILTER, &tdx_msr_test_filter); + TEST_ASSERT(ret =3D=3D 0, + "KVM_X86_SET_MSR_FILTER failed, ret: %i errno: %i (%s)", + ret, errno, strerror(errno)); + + vcpu =3D td_vcpu_add(vm, 0, guest_msr_read); + td_finalize(vm); + + printf("Verifying guest msr reads:\n"); + + printf("\t ... Setting test MSR values\n"); + /* Write arbitrary to the MSRs. */ + vcpu_set_msr(vcpu, MSR_X2APIC_APIC_ICR, 4); + vcpu_set_msr(vcpu, MSR_IA32_MISC_ENABLE, 5); + vcpu_set_msr(vcpu, MSR_IA32_POWER_CTL, 6); + + printf("\t ... Running guest\n"); + td_vcpu_run(vcpu); + TDX_TEST_CHECK_GUEST_FAILURE(vcpu); + data =3D tdx_test_read_64bit_report_from_guest(vcpu); + TEST_ASSERT_EQ(data, 4); + + td_vcpu_run(vcpu); + TDX_TEST_CHECK_GUEST_FAILURE(vcpu); + data =3D tdx_test_read_64bit_report_from_guest(vcpu); + TEST_ASSERT_EQ(data, 5); + + td_vcpu_run(vcpu); + TDX_TEST_CHECK_GUEST_FAILURE(vcpu); + data =3D tdx_test_read_64bit_report_from_guest(vcpu); + TEST_ASSERT_EQ(data, TDG_VP_VMCALL_INVALID_OPERAND); + + td_vcpu_run(vcpu); + TDX_TEST_ASSERT_SUCCESS(vcpu); + + kvm_vm_free(vm); + printf("\t ... PASSED\n"); +} + +/* + * Verifies MSR write functionality. + */ +void guest_msr_write(void) +{ + uint64_t ret; + + ret =3D tdg_vp_vmcall_instruction_wrmsr(MSR_X2APIC_APIC_ICR, 4); + if (ret) + tdx_test_fatal(ret); + + /* We expect this call to fail since MSR_IA32_MISC_ENABLE is read only */ + ret =3D tdg_vp_vmcall_instruction_wrmsr(MSR_IA32_MISC_ENABLE, 5); + if (ret) { + ret =3D tdx_test_report_64bit_to_user_space(ret); + if (ret) + tdx_test_fatal(ret); + } else { + tdx_test_fatal(-99); + } + + + ret =3D tdg_vp_vmcall_instruction_wrmsr(MSR_IA32_POWER_CTL, 6); + if (ret) + tdx_test_fatal(ret); + + tdx_test_success(); +} + +void verify_guest_msr_writes(void) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + uint64_t data; + int ret; + + vm =3D td_create(); + td_initialize(vm, VM_MEM_SRC_ANONYMOUS, 0); + + /* + * Set explicit MSR filter map to control access to the MSR registers + * used in the test. + */ + printf("\t ... Setting test MSR filter\n"); + ret =3D kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR); + TEST_ASSERT(ret, "KVM_CAP_X86_USER_SPACE_MSR is unavailable"); + vm_enable_cap(vm, KVM_CAP_X86_USER_SPACE_MSR, KVM_MSR_EXIT_REASON_FILTER); + + ret =3D kvm_check_cap(KVM_CAP_X86_MSR_FILTER); + TEST_ASSERT(ret, "KVM_CAP_X86_MSR_FILTER is unavailable"); + + ret =3D ioctl(vm->fd, KVM_X86_SET_MSR_FILTER, &tdx_msr_test_filter); + TEST_ASSERT(ret =3D=3D 0, + "KVM_X86_SET_MSR_FILTER failed, ret: %i errno: %i (%s)", + ret, errno, strerror(errno)); + + vcpu =3D td_vcpu_add(vm, 0, guest_msr_write); + td_finalize(vm); + + printf("Verifying guest msr writes:\n"); + + printf("\t ... Running guest\n"); + /* Only the write to MSR_IA32_MISC_ENABLE should trigger an exit */ + td_vcpu_run(vcpu); + TDX_TEST_CHECK_GUEST_FAILURE(vcpu); + data =3D tdx_test_read_64bit_report_from_guest(vcpu); + TEST_ASSERT_EQ(data, TDG_VP_VMCALL_INVALID_OPERAND); + + td_vcpu_run(vcpu); + TDX_TEST_ASSERT_SUCCESS(vcpu); + + printf("\t ... Verifying MSR values writen by guest\n"); + + TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_X2APIC_APIC_ICR), 4); + TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_MISC_ENABLE), 0x1800); + TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_POWER_CTL), 6); + + kvm_vm_free(vm); + printf("\t ... PASSED\n"); +} + + int main(int argc, char **argv) { setbuf(stdout, NULL); @@ -531,6 +738,8 @@ int main(int argc, char **argv) run_in_new_process(&verify_get_td_vmcall_info); run_in_new_process(&verify_guest_writes); run_in_new_process(&verify_guest_reads); + run_in_new_process(&verify_guest_msr_writes); + run_in_new_process(&verify_guest_msr_reads); =20 return 0; } --=20 2.43.0.472.g3155946c3a-goog