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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id v20-20020a170906489400b00a1de512fa24sm6617766ejq.191.2023.12.12.10.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 10:54:18 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: qcom: sm8550: add missing two RX Soundwire ports in configuration Date: Tue, 12 Dec 2023 19:54:15 +0100 Message-Id: <20231212185415.228003-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Qualcomm SM8550 RX Soundwire port configuration was taken from downstream sources ("rx_frame_params_default"), but without two ports. Correct the DTS, even though no practical impact was observed. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong --- Not adding fixes table, as I am not able to identify whether this was actually a bug. --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 17c4f0a7638a..1f06fd33d1ce 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2109,18 +2109,18 @@ swr1: soundwire-controller@6ad0000 { clock-names =3D "iface"; label =3D "RX"; =20 - qcom,din-ports =3D <0>; - qcom,dout-ports =3D <10>; + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; =20 - qcom,ports-sinterval =3D /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xf= f 0xff 0xff 0xff>; - qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0x= ff 0xff 0xff>; - qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0x= ff 0xff 0xff>; - qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xf= f 0xff 0xff>; - qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff= 0xff 0xff>; - qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff= 0xff 0xff 0xff>; - qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 = 0xff 0xff 0xff 0xff>; - qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x0= 0 0xff 0xff 0xff 0xff>; - qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xf= f 0xff 0xff 0xff>; + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xf= f 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x0= 0 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xf= f 0xff 0xff 0xff 0xff 0xff>; =20 #address-cells =3D <2>; #size-cells =3D <0>; --=20 2.34.1