From nobody Wed Dec 17 07:31:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87497C4167B for ; Tue, 12 Dec 2023 16:59:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232634AbjLLQ7J (ORCPT ); Tue, 12 Dec 2023 11:59:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232924AbjLLQ6y (ORCPT ); Tue, 12 Dec 2023 11:58:54 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5FCCB7; Tue, 12 Dec 2023 08:58:57 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3BCGwlba011999; Tue, 12 Dec 2023 10:58:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1702400327; bh=Yp1l87QMy8UzAnUtVPzrggfH8DwMWHj/HeW5IYFg2Wo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OH3e73J7ypwmYq70bM0rLIJv5SY7PE4pKZ+tPtWjL+5f6GC25/Hy1elp67UJtkQPr dhVYyB1R5UkJ4ArTZxOaxslSBFPQjRTCYfz+Ysz/E3TBbk/N0+PD0cZmR43zBdsF9h 1HkgtyuBhwN+1U3ruC/VRpiBSU9LucEJT8ZUL080= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3BCGwlfT037517 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Dec 2023 10:58:47 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 12 Dec 2023 10:58:46 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 12 Dec 2023 10:58:46 -0600 Received: from fllv0122.itg.ti.com (fllv0122.itg.ti.com [10.247.120.72]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3BCGwkgB045579; Tue, 12 Dec 2023 10:58:46 -0600 Received: from localhost (dhcp-10-24-69-31.dhcp.ti.com [10.24.69.31]) by fllv0122.itg.ti.com (8.14.7/8.14.7) with ESMTP id 3BCGwkgo018981; Tue, 12 Dec 2023 10:58:46 -0600 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , Tero Kristo , , , , , MD Danish Anwar Subject: [PATCH v2 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port Date: Tue, 12 Dec 2023 22:28:32 +0530 Message-ID: <20231212165832.3933335-4-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212165832.3933335-1-danishanwar@ti.com> References: <20231212165832.3933335-1-danishanwar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports and 1 x ICSSG1 ports, but it also possible to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration. This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration: - Add label name 'mdio_mux_1' for 'mdio-mux-1' node so that the node 'mdio-mux-1' can be disabled in the overlay using the label name. - disable 2nd CPSW3g port - update CPSW3g pinmuxes to not use RGMII2 - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the shared DP83869 PHY - add and enable ICSSG1 RGMII2 pinmuxes - enable ICSSG1 MII1 port Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../dts/ti/k3-am642-evm-icssg1-dualemac.dtso | 75 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- 3 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 1ac47876bc99..654d9cb6cfea 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-icssg1-dualemac.dtbo =20 # Boards with AM65x SoC k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-base-board-rock= tech-rk101-panel.dtbo @@ -103,6 +104,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am642-evm-icssg1-dualemac-dtbs :=3D \ + k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -113,7 +116,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-csi2-imx219.dtb \ k3-am62a7-sk-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ - k3-am642-tqma64xxl-mbax4xxl-wlan.dtb + k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am642-evm-icssg1-dualemac.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ @@ -121,6 +125,7 @@ DTC_FLAGS_k3-am625-sk +=3D -@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ +DTC_FLAGS_k3-am642-evm +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso b/arc= h/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 000000000000..b2b1a6252e73 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + mdio-mux-2 { + compatible =3D "mdio-mux-multiplexer"; + mux-controls =3D <&mdio_mux>; + mdio-parent-bus =3D <&icssg1_mdio>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + mdio@0 { + reg =3D <0x0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + icssg1_phy2: ethernet-phy@3 { + reg =3D <3>; + tx-internal-delay-ps =3D <250>; + rx-internal-delay-ps =3D <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL= */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0= */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 = */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 = */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3= */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC = */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_C= TL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 =3D <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status =3D "disabled"; +}; + +&mdio_mux_1 { + status =3D "disabled"; +}; + +&icssg1_eth { + pinctrl-0 =3D <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default= >; +}; + +&icssg1_emac1 { + status =3D "okay"; + phy-handle =3D <&icssg1_phy2>; + phy-mode =3D "rgmii-id"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index c08b0223be52..6ae43c12419f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -200,7 +200,7 @@ mdio_mux: mux-controller { mux-gpios =3D <&exp1 12 GPIO_ACTIVE_HIGH>; }; =20 - mdio-mux-1 { + mdio_mux_1: mdio-mux-1 { compatible =3D "mdio-mux-multiplexer"; mux-controls =3D <&mdio_mux>; mdio-parent-bus =3D <&cpsw3g_mdio>; --=20 2.34.1