From nobody Wed Dec 17 09:08:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6FE9C4332F for ; Tue, 12 Dec 2023 16:35:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234973AbjLLQf3 (ORCPT ); Tue, 12 Dec 2023 11:35:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232883AbjLLQfW (ORCPT ); Tue, 12 Dec 2023 11:35:22 -0500 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F72710B; Tue, 12 Dec 2023 08:35:26 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 1185FFF809; Tue, 12 Dec 2023 16:35:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398924; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F1EYqlVYF1fJ33cC2a0Mertg3uhTJJ/NIkImZDHepJg=; b=MJdEjsFpVJ8ioDiw5His3fbeOd2bjIxm4S8sl0YNzERg/it60cuiPt/dVohY1zArlA7RPd J/LPXx9OPkZopk+jPGol+vP9nY2NPZEaFcWrjAF64ytr48w3FwE8H2Tzo7TeFiyHBvI0ML 0gyE6P1LJySEyPz9tEiKyCR/8DY/1ZgtHdpE/i3buNqi1bbeagMTRUNHutjCyfKwGxUgs7 ehc+A4gcnYxxG7Swuz36Zc5coOMuvHIMJrMjOzFkJU73Pcpb6KnZamxbPyxqFM3aO+fQtW EmHU0yGnK9ZMOCnuJ4XWbjp5h1Ies5nloy/gr64dj0CPMpdrAOtuMWjitwmSZg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?UTF-8?q?Th=C3=A9o=20Lebrun?= , Thomas Petazzoni , Gregory CLEMENT , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Florian Fainelli Subject: [PATCH v5 01/22] MIPS: compressed: Use correct instruction for 64 bit code Date: Tue, 12 Dec 2023 17:34:33 +0100 Message-ID: <20231212163459.1923041-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The code clearing BSS already use macro or use correct instruction depending if the CPU is 32 bits or 64 bits. However, a few instructions remained 32 bits only. By using the accurate MACRO, it is now possible to deal with memory address beyond 32 bits. As a side effect, when using 64bits processor, it also divides the loop number needed to clear the BSS by 2. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Florian Fainelli Signed-off-by: Gregory CLEMENT --- arch/mips/boot/compressed/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/h= ead.S index 5795d0af1e1b2..d237a834b85ee 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -25,8 +25,8 @@ /* Clear BSS */ PTR_LA a0, _edata PTR_LA a2, _end -1: sw zero, 0(a0) - addiu a0, a0, 4 +1: PTR_S zero, 0(a0) + PTR_ADDIU a0, a0, PTRSIZE bne a2, a0, 1b =20 PTR_LA a0, (.heap) /* heap address */ --=20 2.42.0