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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECD6.mail.protection.outlook.com (10.167.242.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.18 via Frontend Transport; Tue, 12 Dec 2023 16:02:07 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 12 Dec 2023 10:02:05 -0600 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [RFC PATCH 3/6] iommu/amd: Introduce Guest-ID struct amd_iommu_vminfo Date: Tue, 12 Dec 2023 10:01:36 -0600 Message-ID: <20231212160139.174229-4-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212160139.174229-1-suravee.suthikulpanit@amd.com> References: <20231212160139.174229-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD6:EE_|MW6PR12MB8662:EE_ X-MS-Office365-Filtering-Correlation-Id: e1541d59-45b8-40a6-8f22-08dbfb2bb0d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2023 16:02:07.1801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1541d59-45b8-40a6-8f22-08dbfb2bb0d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8662 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AMD HW-vIOMMU feature requires IOMMU driver to specify a unique 16-bit Guest ID (GID) for each VM. This ID is used to index into various data structures for configuring the hardware. Introduce amd_iommu_vminfo_hash hashtable to store per-vm configuration, which uses 16-bit GID as a hash key along with helper functions. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 6 +++ drivers/iommu/amd/amd_iommu_types.h | 6 +++ drivers/iommu/amd/iommu.c | 66 +++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 4118129f4a24..7783a933ad14 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -182,4 +182,10 @@ void amd_iommu_domain_set_pgtable(struct protection_do= main *domain, struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); =20 extern bool amd_iommu_snp_en; + +/* AMD IOMMU GID */ +int amd_iommu_vminfo_alloc(struct amd_iommu *iommu, struct amd_iommu_vminf= o *vminfo); +void amd_iommu_vminfo_free(struct amd_iommu *iommu, struct amd_iommu_vminf= o *vminfo); +struct amd_iommu_vminfo *amd_iommu_get_vminfo(int gid); + #endif diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 956fd4658a4a..a00731673c50 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* * Maximum number of IOMMUs supported @@ -1053,6 +1054,11 @@ struct amd_irte_ops { void (*clear_allocated)(struct irq_remap_table *, int); }; =20 +struct amd_iommu_vminfo { + u16 gid; + struct hlist_node hnode; +}; + #ifdef CONFIG_IRQ_REMAP extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c41932e9f16a..d18b23ac6357 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,16 @@ LIST_HEAD(acpihid_map); const struct iommu_ops amd_iommu_ops; static const struct iommu_dirty_ops amd_dirty_ops; =20 +/* VMInfo Hashtable */ +#define AMD_IOMMU_VMINFO_HASH_BITS 16 +DEFINE_HASHTABLE(amd_iommu_vminfo_hash, AMD_IOMMU_VMINFO_HASH_BITS); +DEFINE_SPINLOCK(amd_iommu_vminfo_hash_lock); + +/* Global VMID */ +#define AMD_IOMMU_VMID_INVALID (-1U) +static DEFINE_IDA(amd_iommu_global_vmid_ida); +static u32 amd_iommu_latest_gid; + int amd_iommu_max_glx_val =3D -1; =20 /* @@ -101,6 +112,61 @@ static inline bool domain_id_is_per_dev(struct protect= ion_domain *pdom) return (pdom && pdom->pd_mode !=3D PD_MODE_V1); } =20 +int get_vmid(void) +{ + int ret; + + ret =3D ida_alloc_range(&amd_iommu_global_vmid_ida, 1, 0xFFFF, GFP_KERNEL= ); + return ret < 0 ? AMD_IOMMU_VMID_INVALID : ret; +} + +int amd_iommu_vminfo_alloc(struct amd_iommu *iommu, struct amd_iommu_vminf= o *vminfo) +{ + u32 gid; + unsigned long flags; + + spin_lock_irqsave(&amd_iommu_vminfo_hash_lock, flags); + gid =3D amd_iommu_latest_gid =3D get_vmid(); + if (gid =3D=3D AMD_IOMMU_VMID_INVALID) + return -EINVAL; + + pr_debug("%s: gid=3D%u\n", __func__, gid); + vminfo->gid =3D gid; + hash_add(amd_iommu_vminfo_hash, &vminfo->hnode, vminfo->gid); + spin_unlock_irqrestore(&amd_iommu_vminfo_hash_lock, flags); + return 0; +} + +void amd_iommu_vminfo_free(struct amd_iommu *iommu, + struct amd_iommu_vminfo *vminfo) +{ + unsigned long flags; + + pr_debug("%s: gid=3D%u\n", __func__, vminfo->gid); + spin_lock_irqsave(&amd_iommu_vminfo_hash_lock, flags); + hash_del(&vminfo->hnode); + ida_free(&amd_iommu_global_vmid_ida, vminfo->gid); + spin_unlock_irqrestore(&amd_iommu_vminfo_hash_lock, flags); +} + +struct amd_iommu_vminfo *amd_iommu_get_vminfo(int gid) +{ + unsigned long flags; + struct amd_iommu_vminfo *tmp, *ptr =3D NULL; + + spin_lock_irqsave(&amd_iommu_vminfo_hash_lock, flags); + hash_for_each_possible(amd_iommu_vminfo_hash, tmp, hnode, gid) { + if (tmp->gid =3D=3D gid) { + ptr =3D tmp; + break; + } + } + if (!ptr) + pr_debug("%s : gid=3D%u not found\n", __func__, gid); + spin_unlock_irqrestore(&amd_iommu_vminfo_hash_lock, flags); + return ptr; +} + static inline int get_acpihid_device_id(struct device *dev, struct acpihid_map_entry **entry) { --=20 2.34.1