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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id e12-20020a05600c4e4c00b0040b398f0585sm16820693wmq.9.2023.12.12.04.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:56:39 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Abel Vesa Subject: [PATCH 2/2] arm64: dts: qcom: x1e80100: add LPASS LPI pin controller Date: Tue, 12 Dec 2023 13:56:32 +0100 Message-Id: <20231212125632.54021-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212125632.54021-1-krzysztof.kozlowski@linaro.org> References: <20231212125632.54021-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node as part of audio subsystem in Qualcomm X1E80100 SoC. Cc: Abel Vesa Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index aee3dbe753b1..8c18d7f82166 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -2980,6 +2981,20 @@ nsp_noc: interconnect@320c0000 { #interconnect-cells =3D <2>; }; =20 + lpass_tlmm: pinctrl@6e80000 { + compatible =3D "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lp= i-pinctrl"; + reg =3D <0 0x06e80000 0 0x20000>, + <0 0x07250000 0 0x10000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + }; + lpass_ag_noc: interconnect@7e40000 { compatible =3D "qcom,x1e80100-lpass-ag-noc"; reg =3D <0 0x7e40000 0 0xE080>; --=20 2.34.1