From nobody Tue Dec 16 07:09:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11C0EC4167D for ; Tue, 12 Dec 2023 12:42:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346678AbjLLMms (ORCPT ); Tue, 12 Dec 2023 07:42:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232605AbjLLMmr (ORCPT ); Tue, 12 Dec 2023 07:42:47 -0500 Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.220]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9106194; Tue, 12 Dec 2023 04:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=nNmAy t5R/FqSzYRKUKMJgqk+9Njbt4i+66funeH8Iu4=; b=GalmYYAIamECCi0CEbJUG e/S4lOTB5L07QAHGXfCtkgPhWb0Pmg8sKIW7ntL8FBuvr9yGZG5hkDGM9bX/Irom BAX1Al7JhiPj8pcvjjJyxpTv9ufBMxgtREP/HSpOHoDPL/kexqlW1T14hNBILZIn B6l09uSXpZfEC1Vd1Ms1f4= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g0-4 (Coremail) with SMTP id _____wD3H6gwVXhloBDrBA--.14812S2; Tue, 12 Dec 2023 20:42:27 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, sre@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Andy Yan , Krzysztof Kozlowski Subject: [PATCH v4 1/5] dt-bindings: vendor-prefixes: Add Cool Pi Date: Tue, 12 Dec 2023 20:42:23 +0800 Message-Id: <20231212124223.1897314-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212124202.1897238-1-andyshrk@163.com> References: <20231212124202.1897238-1-andyshrk@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3H6gwVXhloBDrBA--.14812S2 X-Coremail-Antispam: 1Uf129KBjvdXoW7JF13Jr1Uuw4UWr1rWF15Jwb_yoWfArb_Xa 1xAw1DZF43JF4Fgw4vyF4xG345Aw12kr9ru3WrtayDCF12yrZrGa97t345Zw1xCF43uas8 Crs3GrWDGrnrGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRAcTQUUUUUU== X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnAFEXlghl9curgAAs+ Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add vendor prefix for Cool Pi(https://cool-pi.com/) Signed-off-by: Andy Yan Acked-by: Krzysztof Kozlowski --- (no changes since v1) Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 309b94c328c8..ddbba46fcbad 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -294,6 +294,8 @@ patternProperties: description: CompuLab Ltd. "^congatec,.*": description: congatec GmbH + "^coolpi,.*": + description: cool-pi.com "^coreriver,.*": description: CORERIVER Semiconductor Co.,Ltd. "^corpro,.*": --=20 2.34.1 From nobody Tue Dec 16 07:09:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C676C4332F for ; Tue, 12 Dec 2023 12:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346700AbjLLMnC (ORCPT ); Tue, 12 Dec 2023 07:43:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232605AbjLLMm7 (ORCPT ); Tue, 12 Dec 2023 07:42:59 -0500 Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.220]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E28D4FF; Tue, 12 Dec 2023 04:43:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=e9peD WR7QL1+BRJUfU0fLvjbdKGtIhqo6TIPfMq2gjE=; b=TfVn22Q4sVE0cZZYRY/qH Tkgqk2IVgovP0QJjfUhGhmPLJ53v+B2ZuZuCpPYYgoQjr5iigIU1i7pdZuOThK+/ kKOqw4MJF2qzjVkUKkolNwhfSZHsHDVw2pkW8I560rLT6dMr1gZ+nZ0CbRTsw9r4 dOANIWl3gDF/fHRXt+ebwg= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g2-3 (Coremail) with SMTP id _____wD3v70+VXhloaTiFQ--.18769S2; Tue, 12 Dec 2023 20:42:41 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, sre@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Andy Yan , Krzysztof Kozlowski Subject: [PATCH v4 2/5] dt-bindings: arm: rockchip: Add Cool Pi 4B Date: Tue, 12 Dec 2023 20:42:37 +0800 Message-Id: <20231212124237.1897378-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212124202.1897238-1-andyshrk@163.com> References: <20231212124202.1897238-1-andyshrk@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3v70+VXhloaTiFQ--.18769S2 X-Coremail-Antispam: 1Uf129KBjvdXoWrtw4xJw18urWUJr1DJr4xWFg_yoWDuFgEka 4xZ3WruFyFvF909w4DAF48GryYkw47KF9rAF1rtF1DC3yDt39xta95t34SkFyxuF43urn3 Crs5JryDGFnxGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRAdb8UUUUUU== X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqAFEXmVOA6bjOAAAsm Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Cool Pi 4B, a SBC powered by RK3588S Signed-off-by: Andy Yan Acked-by: Krzysztof Kozlowski --- (no changes since v2) Changes in v2: - change board compatible from "CoolPi 4 Model B" to "coolpi,pi-4b" Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 5deb66a5c7d9..11d03035f3db 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -95,6 +95,11 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a =20 + - description: Cool Pi 4 Model B + items: + - const: coolpi,pi-4b + - const: rockchip,rk3588s + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards items: - const: edgeble,neural-compute-module-2-io # Edgeble Neural C= ompute Module 2 IO Board --=20 2.34.1 From nobody Tue Dec 16 07:09:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49314C4167B for ; Tue, 12 Dec 2023 12:43:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346729AbjLLMnR (ORCPT ); Tue, 12 Dec 2023 07:43:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346709AbjLLMnP (ORCPT ); Tue, 12 Dec 2023 07:43:15 -0500 Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.219]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 97890F4; Tue, 12 Dec 2023 04:43:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=vsxMH zmYSGP2+7MuUjXf85rG9j1gp9j3u67j2Gc+Dsg=; b=Yzqq8qskR+fjDI+p725/T q2U1duBGGAmGNw/fhSHMsJHrxj9ZzAuoN8uSEMlzc54LZmK7bXn1mUDvX/4nAvGm blHG51yyLnwKrv5xq+xX7pExC4NdU5fTymTEnvXfrrJaMjDLWK1prJFbgyFY1Zmh nIi1++inLR/zYx2AmnP81o= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g1-4 (Coremail) with SMTP id _____wDXX7NOVXhl8xWaFQ--.5747S2; Tue, 12 Dec 2023 20:42:57 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, sre@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Andy Yan Subject: [PATCH v4 3/5] arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B Date: Tue, 12 Dec 2023 20:42:53 +0800 Message-Id: <20231212124253.1897438-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212124202.1897238-1-andyshrk@163.com> References: <20231212124202.1897238-1-andyshrk@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDXX7NOVXhl8xWaFQ--.5747S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfZr48Aw1ftry5Zw1ktFWrKrg_yoW8Zw18Wo Z2vry0yF4YgF43Gr1kJrWDCw1xXrWUGanakF45K3W8Wr4rJwnFyrWayayUWFnrGr10kr1D Z3WrJFy5Cw17C3s5n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RQAwVUUUUU X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEhNEXmVOA6aL7AAAsy Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CoolPi 4B is a rk3588s based SBC. Specification: - Rockchip RK3588S - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - Gigabit ethernet drived by PCIE with RTL8111HS - HDMI Type D out - Mini DP out - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - WIFI/BT module AIC8800 - 40 pin header Signed-off-by: Andy Yan arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B --- (no changes since v3) Changes in v3: - drop ununnecessary property status =3D "okay" for rtc - reorder some nodes alphabetical - remove disabled node Changes in v2: - change board compatible from "CoolPi 4 Model B" to "coolpi,pi-4b" - drop ununnecessary property status =3D "okay" for gpio-led - drop ununnecessary blank line - change node name to rtc for hym8563 arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-coolpi-4b.dts | 823 ++++++++++++++++++ 2 files changed, 824 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 41276ca535de..e59682691eb0 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -109,6 +109,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-plus= .dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-turing-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-khadas-edge2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm6= 4/boot/dts/rockchip/rk3588s-coolpi-4b.dts new file mode 100644 index 000000000000..50b3caae0151 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model =3D "RK3588S CoolPi 4 Model B"; + compatible =3D "coolpi,pi-4b", "rockchip,rk3588s"; + + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdio; + mmc2 =3D &sdmmc; + serial2 =3D &uart2; + }; + + analog-sound { + compatible =3D "audio-graph-card"; + label =3D "rk3588-es8316"; + + widgets =3D "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing =3D "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais =3D <&i2s0_8ch_p0>; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + leds: leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl- =3D <&gpio_leds>; + + led0: led-green { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + led1: led-red { + color =3D ; + function =3D LED_FUNCTION_WLAN; + gpios =3D <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "phy0tx"; + default-state =3D "off"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&hym8563>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usbdcin>; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + vcc3v3_mipi: vcc3v3-mipi-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_mipi"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio =3D <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_u3host_en>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 =3D <&i2c6m3_xfer>; + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "hym8563"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + }; +}; + +&i2c7 { + pinctrl-0 =3D <&i2c7m0_xfer>; + status =3D "okay"; + + es8316: audio-codec@11 { + compatible =3D "everest,es8316"; + reg =3D <0x11>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint =3D <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format =3D "i2s"; + mclk-fs =3D <256>; + remote-endpoint =3D <&es8316_p0_0>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios =3D <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8111_isolate>; + status =3D "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + led { + gpio_leds: gpio-leds { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_u3host_en: vcc5v0-u3host-en { + rockchip,pins =3D <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins =3D <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins =3D <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-0 =3D <&pwm2m1_pins>; + status =3D "okay"; +}; + +&pwm13 { + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm13m2_pins>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&sdio { + max-frequency =3D <150000000>; + no-sd; + no-mmc; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdiom1_pins>,<&wifi_poweren_gpio>; + status =3D "okay"; +}; + +&sdmmc { + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name =3D "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name =3D "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name =3D "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name =3D "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name =3D "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name =3D "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name =3D "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name =3D "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name =3D "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name =3D "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name =3D "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name =3D "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name =3D "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name =3D "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name =3D "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name =3D "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name =3D "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name =3D "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name =3D "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name =3D "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy3_host { + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +/* bt */ +&uart9 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; --=20 2.34.1 From nobody Tue Dec 16 07:09:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55090C4332F for ; Tue, 12 Dec 2023 12:44:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376263AbjLLMoQ (ORCPT ); Tue, 12 Dec 2023 07:44:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346617AbjLLMoO (ORCPT ); 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g4-2 (Coremail) with SMTP id _____wD3_2Z_VXhl6RA1AA--.13259S2; Tue, 12 Dec 2023 20:43:46 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, sre@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Andy Yan , Krzysztof Kozlowski Subject: [PATCH v4 4/5] dt-bindings: arm: rockchip: Add Cool Pi CM5 Date: Tue, 12 Dec 2023 20:43:40 +0800 Message-Id: <20231212124340.1897502-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212124202.1897238-1-andyshrk@163.com> References: <20231212124202.1897238-1-andyshrk@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3_2Z_VXhl6RA1AA--.13259S2 X-Coremail-Antispam: 1Uf129KBjvdXoWrKFW3try5AryxJF4DCF1fXrb_yoWkJFbEka yxZ348CF1FqF9093WDAan7GFy3Jw17Krn7AF4FqF1DCwn8twsIy395t342yFyruF43urn3 Cr4rWryDCFsxGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRAGYLUUUUUU== X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEBZEXmVOA6aFHQABsL Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Cool Pi CM5, a board powered by RK3588 CM5 EVB works with a mother board connect with CM5 Signed-off-by: Andy Yan Acked-by: Krzysztof Kozlowski --- Changes in v4: - Add compatible "coolpi,pi-cm5" for CM5 Changes in v2: - change board compatible from "CoolPi CM5 EVB" to "coolpi,pi-cm5-evb" Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 11d03035f3db..7a81543132a5 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -95,6 +95,13 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a =20 + - description: Cool Pi Compute Module 5(CM5) EVB + items: + - enum: + - coolpi,pi-cm5-evb + - const: coolpi,pi-cm5 + - const: rockchip,rk3588 + - description: Cool Pi 4 Model B items: - const: coolpi,pi-4b --=20 2.34.1 From nobody Tue Dec 16 07:09:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB8D4C4332F for ; Tue, 12 Dec 2023 12:44:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376293AbjLLMom (ORCPT ); Tue, 12 Dec 2023 07:44:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376260AbjLLMoh (ORCPT ); Tue, 12 Dec 2023 07:44:37 -0500 Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.198]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BB641B7; Tue, 12 Dec 2023 04:44:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=dBIQe 4vgkjpANINmABcZ4+cX3MKytsu5ohm8rLasCs0=; b=ntNxlEW6ct9PmWNowlUji 9iDpDFPRzILL+0tOF+sTf/wJ+g9IcRAxnq7eEOhTcKVZYq+W7ubMBxhyrkQEYpuS J8/VA0MC9YZ+6YZ3uLxuFCOv9C9A7B92gIbcL0T54Z7DScSESNdsqqhtkrxRQlcu 5Hustk6esRiY91vIuNBRhs= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g5-1 (Coremail) with SMTP id _____wDnz7mYVXhlUUtMCg--.56823S2; Tue, 12 Dec 2023 20:44:11 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, sre@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Andy Yan Subject: [PATCH v4 5/5] arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB Date: Tue, 12 Dec 2023 20:44:07 +0800 Message-Id: <20231212124407.1897604-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212124202.1897238-1-andyshrk@163.com> References: <20231212124202.1897238-1-andyshrk@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnz7mYVXhlUUtMCg--.56823S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfuFW8XryUXF1fCw4UXFy3twb_yoW8uFy5Jo Z2vry0yF4YgFW3Wr1kJrWDCw1xXrWUGanakF45KF1rWr4rJwnFyFWayayUWF17Gr10kr1k Z3WrJFW5Cw17A3s5n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RQ4SFDUUUU X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqBxEXmVOA6boNwAAs- Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Cool Pi CM5 EVB works as a mother board connect with CM5. CM5 Specification: - Rockchip RK3588 - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - Gigabit ethernet x 1 with PHY YT8531 - Gigabit ethernet x 1 drived by PCIE with YT6801S CM5 EVB Specification: - HDMI Type A out x 2 - HDMI Type D in x 1 - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - PCIE M.2 E Key for Wireless connection - PCIE M.2 M Key for NVME connection - 40 pin header Signed-off-by: Andy Yan --- Changes in v4: - split pi-cm5 as a dtsi Changes in v3: - drop ununnecessary property status =3D "okay" for backlight - reorder some nodes alphabetical - drop ununnecessary blank line Changes in v2: - change board compatible from "CoolPi CM5 EVB" to "coolpi,pi-cm5-evb" arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-coolpi-cm5-evb.dts | 214 ++++++ .../boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 659 ++++++++++++++++++ 3 files changed, 874 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index e59682691eb0..9be8e4830158 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-coolpi-cm5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/= arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts new file mode 100644 index 000000000000..61d01ca7b024 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3588-coolpi-cm5.dtsi" + +/ { + model =3D "RK3588 CoolPi CM5 EVB"; + compatible =3D "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588"; + + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&vcc12v_dcin>; + pwms =3D <&pwm2 0 25000 0>; + enable-gpios =3D <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bl_en>; + }; + + leds: leds { + compatible =3D "gpio-leds"; + + led: led-green { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_lcd: vcc3v3-lcd-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_lcd"; + enable-active-high; + gpio =3D <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcdpwr_en>; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg_pwren>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +/* M.2 E-Key */ +&pcie2x1l1 { + reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; + status =3D "okay"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x2 { + reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_sys>; + status =3D "okay"; +}; + +/* M.2 M-Key ssd */ +&pcie3x4 { + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_sys>; + status =3D "okay"; +}; + +&pinctrl { + lcd { + lcdpwr_en: lcdpwr-en { + rockchip,pins =3D <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bl_en: bl-en { + rockchip,pins =3D <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + bt_pwron: bt-pwron { + rockchip,pins =3D <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_clkreq: pcie-clkreq { + rockchip,pins =3D <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_rst: pcie-rst { + rockchip,pins =3D <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_pwron: wifi-pwron { + rockchip,pins =3D <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_wake: pcie-wake { + rockchip,pins =3D <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status =3D "okay"; +}; + +&sata1 { + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi new file mode 100644 index 000000000000..fcdc3e7a4351 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -0,0 +1,659 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible =3D "coolpi,pi-cm5", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdio; + mmc2 =3D &sdmmc; + serial2 =3D &uart2; + }; + + analog-sound { + compatible =3D "audio-graph-card"; + label =3D "rk3588-es8316"; + + widgets =3D "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing =3D "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais =3D <&i2s0_8ch_p0>; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + avdd0v75_pcie30: avdd0v75-pcie30-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd0v75_pcie30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + vin-supply =3D <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: avdd1v8-pcie30-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-rxid"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names =3D "default"; + rx_delay =3D <0x00>; + tx_delay =3D <0x43>; + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "hym8563"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 =3D <&i2c7m0_xfer>; + status =3D "okay"; + + es8316: audio-codec@11 { + compatible =3D "everest,es8316"; + reg =3D <0x11>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint =3D <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format =3D "i2s"; + mclk-fs =3D <256>; + remote-endpoint =3D <&es8316_p0_0>; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C/H */ + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&yt8531_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +/* ethernet */ +&pcie2x1l2 { + reset-gpios =3D <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&yt6801_isolate>; + status =3D "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt6801 { + yt6801_isolate: yt6801-isolate { + rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt8531 { + yt8531_rst: yt8531-rst { + rockchip,pins =3D <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply =3D <&vcc_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&sdmmc { + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + status =3D "okay"; + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + num-cs =3D <1>; + + pmic@0 { + compatible =3D "rockchip,rk806"; + spi-max-frequency =3D <1000000>; + reg =3D <0x0>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_2v0_pldo_s3>; + vcc14-supply =3D <&vcc_2v0_pldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; + + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; --=20 2.34.1