From nobody Fri Sep 20 07:41:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09186C38147 for ; Tue, 12 Dec 2023 12:21:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346526AbjLLMU7 (ORCPT ); Tue, 12 Dec 2023 07:20:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232539AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6076F5; Tue, 12 Dec 2023 04:20:11 -0800 (PST) X-UUID: c66879d698e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=K4w5up8ZLqgyPQD8H2AboWYB5hZ/MbRF9/Caa0P/nFY=; b=HhuCOvW4IhLy5vj+kqHvm32ou+xjclkW82NhRao1Nuj8UBZyP/CKXGr+xru2a7713lAACW3AzQ4KPDRcuKus9FSjLDq5fKBWxU6Vi/x9WCUOuDnVNd1EpxuIteQ6aerOwNSDdOHiyPs/i2FIYkR834XhLc5wMs/Cli80cYxX72s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:2491e0dc-58ac-4849-9ac7-9c3af3b7cdde,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:383b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c66879d698e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1401706049; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 06/17] drm/mediatek: Support alpha blending in OVL Date: Tue, 12 Dec 2023 20:19:46 +0800 Message-ID: <20231212121957.19231-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support premultiply and coverage alpha blending in Overlay. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 73 +++++++++++++++++-------- 1 file changed, 51 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 5aaf4342cdbd..66074c2d917c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -39,6 +39,7 @@ #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) +#define OVL_CONST_BLEND BIT(28) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -52,13 +53,16 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) =20 -#define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) -#define OVL_CON_CLRFMT_RGB (1 << 12) -#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) -#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) -#define OVL_CON_CLRFMT_UYVY (4 << 12) -#define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_CLRFMT_MAN BIT(23) +#define OVL_CON_BYTE_SWAP BIT(24) +#define OVL_CON_RGB_SWAP BIT(25) +#define OVL_CON_CLRFMT_RGB (1 << 12) +#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) +#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_CLRFMT= _MAN) +#define OVL_CON_CLRFMT_UYVY (4 << 12) +#define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -208,14 +212,12 @@ void mtk_ovl_clk_disable(struct device *dev) void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int reg =3D readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); =20 - if (ovl->data->smi_id_en) { - unsigned int reg; + if (ovl->data->smi_id_en) + reg |=3D OVL_LAYER_SMI_ID_EN; =20 - reg =3D readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); - reg =3D reg | OVL_LAYER_SMI_ID_EN; - writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); - } + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } =20 @@ -274,7 +276,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w, if (w !=3D 0 && h !=3D 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_= OVL_ROI_BGCLR); + + /* + * The background color should be opaque black (ARGB), + * otherwise there will be no effect with alpha blend + */ + mtk_ddp_write_relaxed(cmdq_pkt, 0xff000000, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_ROI_BGCLR); =20 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); @@ -357,7 +365,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int= idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -376,18 +385,30 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: - return OVL_CON_CLRFMT_ARGB8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + return OVL_CON_BYTE_SWAP | + (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888); case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: - return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_RGB_SWAP | + (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888); case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: @@ -408,6 +429,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int blend_mode =3D state->base.pixel_blend_mode; + unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; union overlay_pitch { @@ -425,9 +448,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |=3D OVL_CON_AEN | OVL_CON_ALPHA; + con =3D ovl_fmt_convert(ovl, fmt, blend_mode); + if (state->base.fb) { + con |=3D OVL_CON_AEN; + con |=3D state->base.alpha & OVL_CON_ALPHA; + } + + if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) + ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; @@ -444,8 +473,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq= _reg, ovl->regs, - DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pi= xel_alpha, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, --=20 2.18.0