From nobody Fri Dec 19 14:44:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DCCFC4167B for ; Mon, 11 Dec 2023 09:44:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234620AbjLKJo1 (ORCPT ); Mon, 11 Dec 2023 04:44:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234589AbjLKJoZ (ORCPT ); Mon, 11 Dec 2023 04:44:25 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D022CE for ; Mon, 11 Dec 2023 01:44:31 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-54dccf89cfdso5385384a12.0 for ; Mon, 11 Dec 2023 01:44:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702287870; x=1702892670; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qp+2/AFV5zmaxe9luf0MNfHGuX9N1n8phVhdPWTto6c=; b=PqGsMHqrjIbOG1jeGkSr5qWqzFYVWDDMX2+ZplyFD6V1BP1jeJixc6eJG8wanxalza CXiDQ3MfUJ9EAWTNColLMQPgdvHbWNX/O1K4KIG3EqHS91lfFYxvlAQuvkw3myANLlM3 +ojd0pcWPb0Uk2WrHFdEekbv3bg4U2xQxPaxpPruXY+zEcas+OP+r+YfKQSMt0484S6g IyP9i2L6jjQEo3HC0srDA2vZQWoyQ0Z1PB6cc2BE/KxbMXQKVsoRnx3vsfhCllXlJ7vn VXkirjB5gUuq0Fu1vE88MBFD0JntwDoDy69Aiks7/ee/a9zHigXa21jqUHeIbiRhqEQZ jwUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702287870; x=1702892670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qp+2/AFV5zmaxe9luf0MNfHGuX9N1n8phVhdPWTto6c=; b=rs6GZM+xuL1pxP21uT3taGqAdf7mZe5SjYFEMVLnt5iZIiU66YTE2L1Pv4D7GA5BLX IYJmvn/Ll9JbI6+ztwbZ6aC5Atqfzeuo2zO8rWvsSWI4VcqHVs8MjlBMpUgd9j3FXPaE 4UQ/P/x/P2Wx7nk0D6D8mMJz7MBNFmAmstFdHlLJZ/G+WvqrKfCasQ1zCw0zzB1jfQIB YF7tXV99IOzry6ZMrNjIdp6JIvdnk/Ge/4alIcHwYYDXA7d/ZK+GBiMYjSue8YABDRoj CI/GoJT5KVrDXXr8ur5gxBaaYRkbjYGixdiQHjYH5w0zzgenJf1KI7rsfN/T+oHFmLG/ VC1A== X-Gm-Message-State: AOJu0YwHaAK39W8733Vi94mgztxBdIrXrV/xbu92N6butfOP3KHLtec2 rWUIuZHSenGLGTWg05RGsLY= X-Google-Smtp-Source: AGHT+IEaDoQFpPnxjlxeSUTzsAQavayOPPXdg/d408f0Mv7GQd3onKpiAY7YqVStGjAikZKqi4sBkw== X-Received: by 2002:a50:c908:0:b0:551:12f7:84e with SMTP id o8-20020a50c908000000b0055112f7084emr996214edh.28.1702287869354; Mon, 11 Dec 2023 01:44:29 -0800 (PST) Received: from andrea.wind3.hub ([31.189.124.152]) by smtp.gmail.com with ESMTPSA id if3-20020a0564025d8300b0054afcab0af2sm3463505edb.59.2023.12.11.01.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 01:44:28 -0800 (PST) From: Andrea Parri To: mathieu.desnoyers@efficios.com, paulmck@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: mmaas@google.com, hboehm@google.com, striker@us.ibm.com, charlie@rivosinc.com, rehn@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrea Parri Subject: [PATCH v2 1/4] membarrier: riscv: Add full memory barrier in switch_mm() Date: Mon, 11 Dec 2023 10:44:11 +0100 Message-Id: <20231211094414.8078-2-parri.andrea@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211094414.8078-1-parri.andrea@gmail.com> References: <20231211094414.8078-1-parri.andrea@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The membarrier system call requires a full memory barrier after storing to rq->curr, before going back to user-space. The barrier is only needed when switching between processes: the barrier is implied by mmdrop() when switching from kernel to userspace, and it's not needed when switching from userspace to kernel. Rely on the feature/mechanism ARCH_HAS_MEMBARRIER_CALLBACKS and on the primitive membarrier_arch_switch_mm(), already adopted by the PowerPC architecture, to insert the required barrier. Fixes: fab957c11efe2f ("RISC-V: Atomic and Locking Code") Signed-off-by: Andrea Parri Reported-by: Mathieu Desnoyers Reviewed-by: Mathieu Desnoyers --- MAINTAINERS | 2 +- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/membarrier.h | 29 +++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 2 ++ kernel/sched/core.c | 5 +++-- 5 files changed, 36 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/include/asm/membarrier.h diff --git a/MAINTAINERS b/MAINTAINERS index e2c6187a3ac80..a9166d82ffced 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13807,7 +13807,7 @@ M: Mathieu Desnoyers M: "Paul E. McKenney" L: linux-kernel@vger.kernel.org S: Supported -F: arch/powerpc/include/asm/membarrier.h +F: arch/*/include/asm/membarrier.h F: include/uapi/linux/membarrier.h F: kernel/sched/membarrier.c =20 diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 95a2a06acc6a6..f7db95097caf1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,7 @@ config RISCV select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV + select ARCH_HAS_MEMBARRIER_CALLBACKS select ARCH_HAS_MMIOWB select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PMEM_API diff --git a/arch/riscv/include/asm/membarrier.h b/arch/riscv/include/asm/m= embarrier.h new file mode 100644 index 0000000000000..4be218fa03b14 --- /dev/null +++ b/arch/riscv/include/asm/membarrier.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_MEMBARRIER_H +#define _ASM_RISCV_MEMBARRIER_H + +static inline void membarrier_arch_switch_mm(struct mm_struct *prev, + struct mm_struct *next, + struct task_struct *tsk) +{ + /* + * Only need the full barrier when switching between processes. + * Barrier when switching from kernel to userspace is not + * required here, given that it is implied by mmdrop(). Barrier + * when switching from userspace to kernel is not needed after + * store to rq->curr. + */ + if (IS_ENABLED(CONFIG_SMP) && + likely(!(atomic_read(&next->membarrier_state) & + (MEMBARRIER_STATE_PRIVATE_EXPEDITED | + MEMBARRIER_STATE_GLOBAL_EXPEDITED)) || !prev)) + return; + + /* + * The membarrier system call requires a full memory barrier + * after storing to rq->curr, before going back to user-space. + */ + smp_mb(); +} + +#endif /* _ASM_RISCV_MEMBARRIER_H */ diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de61342..ba8eb3944687c 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -323,6 +323,8 @@ void switch_mm(struct mm_struct *prev, struct mm_struct= *next, if (unlikely(prev =3D=3D next)) return; =20 + membarrier_arch_switch_mm(prev, next, task); + /* * Mark the current MM context as inactive, and the next as * active. This is at least used by the icache flushing diff --git a/kernel/sched/core.c b/kernel/sched/core.c index a708d225c28e8..711dc753f7216 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -6670,8 +6670,9 @@ static void __sched notrace __schedule(unsigned int s= ched_mode) * * Here are the schemes providing that barrier on the * various architectures: - * - mm ? switch_mm() : mmdrop() for x86, s390, sparc, PowerPC. - * switch_mm() rely on membarrier_arch_switch_mm() on PowerPC. + * - mm ? switch_mm() : mmdrop() for x86, s390, sparc, PowerPC, + * RISC-V. switch_mm() relies on membarrier_arch_switch_mm() + * on PowerPC and on RISC-V. * - finish_lock_switch() for weakly-ordered * architectures where spin_unlock is a full barrier, * - switch_to() for arm64 (weakly-ordered, spin_unlock --=20 2.34.1