From nobody Sun Nov 10 08:14:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64CD6C10F13 for ; Mon, 11 Dec 2023 08:53:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234069AbjLKIxW (ORCPT ); Mon, 11 Dec 2023 03:53:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229908AbjLKIxO (ORCPT ); Mon, 11 Dec 2023 03:53:14 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A364EC4; Mon, 11 Dec 2023 00:53:16 -0800 (PST) X-UUID: b649325c980211eea5db2bebc7c28f94-20231211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=N8a2skbn3ldUXfGVBRWQ1u0Qf2+Xz3OWdG8kf2ohLgc=; b=RNXKMyg3ZOCfIqHfxthJKg++dBfxLIQNc8+iXnJs8p+p4Ooxpm+ALD6eYJ5R0ViYlc2Jp6GRN07Hp2LaDpO8FXqRbnLaDJhibwxByqhhbHphIZLoVKI3OHFtJjvS8cOPdg0TBphLWh7YRwMYP4bqoptAKjk7+0ZlgXvS/kAlKsU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:d14b24b7-0931-4916-92c8-a68885c58a0a,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:dd2887fd-4a48-46e2-b946-12f04f20af8c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: b649325c980211eea5db2bebc7c28f94-20231211 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1958292593; Mon, 11 Dec 2023 16:53:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Dec 2023 16:53:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Dec 2023 16:53:06 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Marc Zyngier CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH v2 1/3] PCI: mediatek: Allocate MSI address with dmam_alloc_coherent() Date: Mon, 11 Dec 2023 16:52:54 +0800 Message-ID: <20231211085256.31292-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211085256.31292-1-jianjun.wang@mediatek.com> References: <20231211085256.31292-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.452000-8.000000 X-TMASE-MatchedRID: YlUeb+P3LGlBHBd/Q+ztBwPZZctd3P4BIaVkFIrQFhtb6PBUqmq+UlYu mEk/UtlHxvP5MvmYpyBTc0C6OSQvz8pFJHzzp4rS58dk5sbwmyjGYnoF/CTeZVSOymiJfTYXlwW f7/4SyDtrg8FCypqvfGmevJVqJe6AHxPMjOKY7A8LbigRnpKlKZvjAepGmdoOjSE7r38ccucfAi JtYJYn7WCx0B/Tk9JmY616mIENddzqpQj72dAQYgHduAz87L4zdUVIHoasg2idNYuO1rAFqL0we Uq5YYes8jae4OD13tAV7Mc+rowcVKtX/F0pBwVJjSV5hDFby7ZnIxZyJs78kg== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.452000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3399B1CCA37B4999E57B22197D5592ECC7DE562E04091DEA609953BF1EF284B22000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use dmam_alloc_coherent() to allocate the MSI address, instead of using virt_to_phys(). Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 66a8f73296fc..2fb9e44369f8 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -178,6 +178,7 @@ struct mtk_pcie_soc { * @phy: pointer to PHY control block * @slot: port slot * @irq: GIC irq + * @msg_addr: MSI message address * @irq_domain: legacy INTx IRQ domain * @inner_domain: inner IRQ domain * @msi_domain: MSI IRQ domain @@ -198,6 +199,7 @@ struct mtk_pcie_port { struct phy *phy; u32 slot; int irq; + dma_addr_t msg_addr; struct irq_domain *irq_domain; struct irq_domain *inner_domain; struct irq_domain *msi_domain; @@ -394,12 +396,10 @@ static struct pci_ops mtk_pcie_ops_v2 =3D { static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct mtk_pcie_port *port =3D irq_data_get_irq_chip_data(data); - phys_addr_t addr; =20 /* MT2712/MT7622 only support 32-bit MSI addresses */ - addr =3D virt_to_phys(port->base + PCIE_MSI_VECTOR); msg->address_hi =3D 0; - msg->address_lo =3D lower_32_bits(addr); + msg->address_lo =3D lower_32_bits(port->msg_addr); =20 msg->data =3D data->hwirq; =20 @@ -494,6 +494,14 @@ static struct msi_domain_info mtk_msi_domain_info =3D { static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) { struct fwnode_handle *fwnode =3D of_node_to_fwnode(port->pcie->dev->of_no= de); + void *msi_vaddr; + + msi_vaddr =3D dmam_alloc_coherent(port->pcie->dev, sizeof(dma_addr_t), &p= ort->msg_addr, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(port->pcie->dev, "failed to alloc and map MSI address\n"); + return -ENOMEM; + } =20 mutex_init(&port->lock); =20 @@ -501,6 +509,7 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pci= e_port *port) &msi_domain_ops, port); if (!port->inner_domain) { dev_err(port->pcie->dev, "failed to create IRQ domain\n"); + dmam_free_coherent(port->pcie->dev, sizeof(dma_addr_t), msi_vaddr, port-= >msg_addr); return -ENOMEM; } =20 @@ -508,6 +517,7 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pci= e_port *port) port->inner_domain); if (!port->msi_domain) { dev_err(port->pcie->dev, "failed to create MSI domain\n"); + dmam_free_coherent(port->pcie->dev, sizeof(dma_addr_t), msi_vaddr, port-= >msg_addr); irq_domain_remove(port->inner_domain); return -ENOMEM; } @@ -518,10 +528,8 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pc= ie_port *port) static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) { u32 val; - phys_addr_t msg_addr; =20 - msg_addr =3D virt_to_phys(port->base + PCIE_MSI_VECTOR); - val =3D lower_32_bits(msg_addr); + val =3D lower_32_bits(port->msg_addr); writel(val, port->base + PCIE_IMSI_ADDR); =20 val =3D readl(port->base + PCIE_INT_MASK); @@ -588,7 +596,7 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_por= t *port, if (IS_ENABLED(CONFIG_PCI_MSI)) { ret =3D mtk_pcie_allocate_msi_domains(port); if (ret) - return ret; + dev_warn(dev, "no MSI supported, only INTx available\n"); } =20 return 0; @@ -732,7 +740,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_por= t *port) val &=3D ~INTX_MASK; writel(val, port->base + PCIE_INT_MASK); =20 - if (IS_ENABLED(CONFIG_PCI_MSI)) + if (IS_ENABLED(CONFIG_PCI_MSI) && port->msi_domain) mtk_pcie_enable_msi(port); =20 /* Set AHB to PCIe translation windows */ --=20 2.18.0 From nobody Sun Nov 10 08:14:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA01CC4167B for ; Mon, 11 Dec 2023 08:53:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231563AbjLKIxP (ORCPT ); Mon, 11 Dec 2023 03:53:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229654AbjLKIxN (ORCPT ); Mon, 11 Dec 2023 03:53:13 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2864CB6; 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Mon, 11 Dec 2023 16:53:09 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Dec 2023 16:53:08 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Dec 2023 16:53:07 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Marc Zyngier CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH v2 2/3] PCI: mediatek-gen3: Do not break probe flow when MSI init fails Date: Mon, 11 Dec 2023 16:52:55 +0800 Message-ID: <20231211085256.31292-3-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211085256.31292-1-jianjun.wang@mediatek.com> References: <20231211085256.31292-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since INTx can still work, the driver probe flow should not be broken by MSI initialization failures. Additionally, moving the MSI initialization code into a single function enhances readability. Fixes: 1bdafba538be ("PCI: mediatek-gen3: Add MSI support") Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 68 ++++++++++----------- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index c1ae3d19ec9a..c6a6876d233a 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -649,59 +649,51 @@ static const struct irq_domain_ops intx_domain_ops = =3D { .map =3D mtk_pcie_intx_map, }; =20 -static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) +static int mtk_pcie_init_msi(struct mtk_gen3_pcie *pcie) { struct device *dev =3D pcie->dev; - struct device_node *intc_node, *node =3D dev->of_node; - int ret; - - raw_spin_lock_init(&pcie->irq_lock); - - /* Setup INTx */ - intc_node =3D of_get_child_by_name(node, "interrupt-controller"); - if (!intc_node) { - dev_err(dev, "missing interrupt-controller node\n"); - return -ENODEV; - } - - pcie->intx_domain =3D irq_domain_add_linear(intc_node, PCI_NUM_INTX, - &intx_domain_ops, pcie); - if (!pcie->intx_domain) { - dev_err(dev, "failed to create INTx IRQ domain\n"); - ret =3D -ENODEV; - goto out_put_node; - } + struct device_node *node =3D dev->of_node; =20 - /* Setup MSI */ mutex_init(&pcie->lock); =20 pcie->msi_bottom_domain =3D irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, &mtk_msi_bottom_domain_ops, pcie); if (!pcie->msi_bottom_domain) { dev_err(dev, "failed to create MSI bottom domain\n"); - ret =3D -ENODEV; - goto err_msi_bottom_domain; + return -ENODEV; } =20 - pcie->msi_domain =3D pci_msi_create_irq_domain(dev->fwnode, - &mtk_msi_domain_info, + pcie->msi_domain =3D pci_msi_create_irq_domain(dev->fwnode, &mtk_msi_doma= in_info, pcie->msi_bottom_domain); if (!pcie->msi_domain) { dev_err(dev, "failed to create MSI domain\n"); - ret =3D -ENODEV; - goto err_msi_domain; + irq_domain_remove(pcie->msi_bottom_domain); + return -ENODEV; } =20 - of_node_put(intc_node); return 0; +} =20 -err_msi_domain: - irq_domain_remove(pcie->msi_bottom_domain); -err_msi_bottom_domain: - irq_domain_remove(pcie->intx_domain); -out_put_node: +static int mtk_pcie_init_intx(struct mtk_gen3_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct device_node *intc_node, *node =3D dev->of_node; + + intc_node =3D of_get_child_by_name(node, "interrupt-controller"); + if (!intc_node) { + dev_err(dev, "missing interrupt-controller node\n"); + return -ENODEV; + } + + pcie->intx_domain =3D irq_domain_add_linear(intc_node, PCI_NUM_INTX, + &intx_domain_ops, pcie); of_node_put(intc_node); - return ret; + if (!pcie->intx_domain) { + dev_err(dev, "failed to create INTx IRQ domain\n"); + return -ENODEV; + } + + return 0; } =20 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) @@ -774,10 +766,16 @@ static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *p= cie) struct platform_device *pdev =3D to_platform_device(dev); int err; =20 - err =3D mtk_pcie_init_irq_domains(pcie); + raw_spin_lock_init(&pcie->irq_lock); + + err =3D mtk_pcie_init_intx(pcie); if (err) return err; =20 + err =3D mtk_pcie_init_msi(pcie); + if (err) + dev_warn(dev, "no MSI supported, only INTx available\n"); + pcie->irq =3D platform_get_irq(pdev, 0); if (pcie->irq < 0) return pcie->irq; --=20 2.18.0 From nobody Sun Nov 10 08:14:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D50C4C10DC3 for ; Mon, 11 Dec 2023 08:53:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234028AbjLKIxT (ORCPT ); Mon, 11 Dec 2023 03:53:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbjLKIxO (ORCPT ); Mon, 11 Dec 2023 03:53:14 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FF6FD2; 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Mon, 11 Dec 2023 16:53:10 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Dec 2023 16:53:09 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Dec 2023 16:53:08 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Marc Zyngier CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH v2 3/3] PCI: mediatek-gen3: Allocate MSI address with dmam_alloc_coherent() Date: Mon, 11 Dec 2023 16:52:56 +0800 Message-ID: <20231211085256.31292-4-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211085256.31292-1-jianjun.wang@mediatek.com> References: <20231211085256.31292-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use dmam_alloc_coherent() to allocate the MSI address, instead of using static physical address. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 72 ++++++++++++--------- 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index c6a6876d233a..7cfd7ef9ad95 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -120,7 +120,6 @@ struct mtk_msi_set { * struct mtk_gen3_pcie - PCIe port information * @dev: pointer to PCIe device * @base: IO mapped register base - * @reg_base: physical register base * @mac_reset: MAC reset control * @phy_reset: PHY reset control * @phy: PHY controller block @@ -139,7 +138,6 @@ struct mtk_msi_set { struct mtk_gen3_pcie { struct device *dev; void __iomem *base; - phys_addr_t reg_base; struct reset_control *mac_reset; struct reset_control *phy_reset; struct phy *phy; @@ -309,24 +307,8 @@ static int mtk_pcie_set_trans_table(struct mtk_gen3_pc= ie *pcie, =20 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) { - int i; u32 val; =20 - for (i =3D 0; i < PCIE_MSI_SET_NUM; i++) { - struct mtk_msi_set *msi_set =3D &pcie->msi_sets[i]; - - msi_set->base =3D pcie->base + PCIE_MSI_SET_BASE_REG + - i * PCIE_MSI_SET_OFFSET; - msi_set->msg_addr =3D pcie->reg_base + PCIE_MSI_SET_BASE_REG + - i * PCIE_MSI_SET_OFFSET; - - /* Configure the MSI capture address */ - writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); - writel_relaxed(upper_32_bits(msi_set->msg_addr), - pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + - i * PCIE_MSI_SET_ADDR_HI_OFFSET); - } - val =3D readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); val |=3D PCIE_MSI_SET_ENABLE; writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); @@ -653,6 +635,29 @@ static int mtk_pcie_init_msi(struct mtk_gen3_pcie *pci= e) { struct device *dev =3D pcie->dev; struct device_node *node =3D dev->of_node; + struct mtk_msi_set *msi_set; + void *msg_vaddr[PCIE_MSI_SET_NUM]; + int i, j, ret =3D -ENODEV; + + for (i =3D 0; i < PCIE_MSI_SET_NUM; i++) { + msi_set =3D &pcie->msi_sets[i]; + + msi_set->base =3D pcie->base + PCIE_MSI_SET_BASE_REG + + i * PCIE_MSI_SET_OFFSET; + + msg_vaddr[i] =3D dmam_alloc_coherent(dev, sizeof(dma_addr_t), + &msi_set->msg_addr, GFP_KERNEL); + if (!msg_vaddr[i]) { + dev_err(dev, "failed to alloc and map MSI address for set %d\n", i); + ret =3D -ENOMEM; + goto err_alloc_addr; + } + + /* Configure the MSI capture address */ + writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); + writel_relaxed(upper_32_bits(msi_set->msg_addr), pcie->base + + PCIE_MSI_SET_ADDR_HI_BASE + i * PCIE_MSI_SET_ADDR_HI_OFFSET); + } =20 mutex_init(&pcie->lock); =20 @@ -660,18 +665,24 @@ static int mtk_pcie_init_msi(struct mtk_gen3_pcie *pc= ie) &mtk_msi_bottom_domain_ops, pcie); if (!pcie->msi_bottom_domain) { dev_err(dev, "failed to create MSI bottom domain\n"); - return -ENODEV; + goto err_alloc_addr; } =20 pcie->msi_domain =3D pci_msi_create_irq_domain(dev->fwnode, &mtk_msi_doma= in_info, pcie->msi_bottom_domain); - if (!pcie->msi_domain) { - dev_err(dev, "failed to create MSI domain\n"); - irq_domain_remove(pcie->msi_bottom_domain); - return -ENODEV; + if (pcie->msi_domain) + return 0; + + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(pcie->msi_bottom_domain); + +err_alloc_addr: + for (j =3D 0; j < i; j++) { + msi_set =3D &pcie->msi_sets[j]; + dmam_free_coherent(dev, sizeof(dma_addr_t), msg_vaddr[j], msi_set->msg_a= ddr); } =20 - return 0; + return ret; } =20 static int mtk_pcie_init_intx(struct mtk_gen3_pcie *pcie) @@ -789,20 +800,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *= pcie) { struct device *dev =3D pcie->dev; struct platform_device *pdev =3D to_platform_device(dev); - struct resource *regs; int ret; =20 - regs =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); - if (!regs) - return -EINVAL; - pcie->base =3D devm_ioremap_resource(dev, regs); + pcie->base =3D devm_platform_ioremap_resource_byname(pdev, "pcie-mac"); if (IS_ERR(pcie->base)) { dev_err(dev, "failed to map register base\n"); return PTR_ERR(pcie->base); } =20 - pcie->reg_base =3D regs->start; - pcie->phy_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy"); if (IS_ERR(pcie->phy_reset)) { ret =3D PTR_ERR(pcie->phy_reset); @@ -1013,6 +1018,11 @@ static void mtk_pcie_irq_restore(struct mtk_gen3_pci= e *pcie) for (i =3D 0; i < PCIE_MSI_SET_NUM; i++) { struct mtk_msi_set *msi_set =3D &pcie->msi_sets[i]; =20 + /* Configure the MSI capture address */ + writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); + writel_relaxed(upper_32_bits(msi_set->msg_addr), pcie->base + + PCIE_MSI_SET_ADDR_HI_BASE + i * PCIE_MSI_SET_ADDR_HI_OFFSET); + writel_relaxed(msi_set->saved_irq_state, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); } --=20 2.18.0