From nobody Wed Dec 17 00:19:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5680C4167B for ; Fri, 8 Dec 2023 16:14:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1574452AbjLHQOD (ORCPT ); Fri, 8 Dec 2023 11:14:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1574102AbjLHQNT (ORCPT ); Fri, 8 Dec 2023 11:13:19 -0500 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 414071BCD; Fri, 8 Dec 2023 08:13:10 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 9E89C4000E; Fri, 8 Dec 2023 16:13:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702051989; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nfmmkPLG/ll5NZfOYiII8ssFiuAZWR9wcDBKqL8DiFA=; b=fDYLQNH1IyMnxW/+wkjZnJIhVhfRrB7BQOJxQZ3yPqyz79giZbTLciVXvf9f1flrp7ahyF OT5CFnRQhQGqQRbOi996suQKCivj57fmIPN/auzXjCPaECCIIqDYWjucfAEtET/3pBzQxx KjxwHtm/05LpwradsOC0UyibI8JhaVdRQQvPZzFxmyd0+46eLwlpIP+PkiJ8GJQoeUjwO0 xFD4BsGboCaLcOTbC19ERwDZLOvsing4DQDRXJzX8omNmf5dEhQyCMx0SU1HFxtm49fHHw foUdHdItwJ/9sj6aNBgcSLlC+QTPXIKdq2cDT93N7PTVXchs70o6XpyWI2FtGg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?UTF-8?q?Th=C3=A9o=20Lebrun?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v4 19/22] MIPS: mobileye: Add EyeQ5 dtsi Date: Fri, 8 Dec 2023 17:12:35 +0100 Message-ID: <20231208161249.1827174-20-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208161249.1827174-1-gregory.clement@bootlin.com> References: <20231208161249.1827174-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/Makefile | 1 + .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 292 ++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 134 ++++++++ 3 files changed, 427 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 928f38a79dff9..edb8e8dee7583 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) +=3D lantiq subdir-$(CONFIG_MACH_LOONGSON64) +=3D loongson subdir-$(CONFIG_SOC_VCOREIII) +=3D mscc subdir-$(CONFIG_MIPS_MALTA) +=3D mti +subdir-$(CONFIG_SOC_EYEQ5) +=3D mobileye subdir-$(CONFIG_LEGACY_BOARD_SEAD3) +=3D mti subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) +=3D ni subdir-$(CONFIG_MACH_PIC32) +=3D pic32 diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mip= s/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 0000000000000..78f5533a95c67 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll-cpu { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1500000000>; + }; + + pll_vdi: pll-vdi { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1280000000>; + }; + + pll_per: pll-per { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <2000000000>; + }; + + pll_ddr0: pll-ddr0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1857210000>; + }; + + pll_ddr1: pll-ddr1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ-cpu { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_cpu>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_cpu>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + cpc_clk: cpc-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + core0_clk: core0-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + core1_clk: core1-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + core2_clk: core2-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + core3_clk: core3-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + cm_clk: cm-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + mem_clk: mem-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&si_css0_ref_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + occ_isram: occ-isram { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_cpu>; + #clock-cells =3D <0>; + clock-div =3D <2>; + clock-mult =3D <1>; + }; + isram_clk: isram-clk { /* gate ClkRstGen_isram */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_isram>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + occ_dbu: occ-dbu { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_cpu>; + #clock-cells =3D <0>; + clock-div =3D <10>; + clock-mult =3D <1>; + }; + si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_dbu>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ-vdi { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_vdi>; + #clock-cells =3D <0>; + clock-div =3D <2>; + clock-mult =3D <1>; + }; + vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_vdi>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + occ_can_ser: occ-can-ser { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_vdi>; + #clock-cells =3D <0>; + clock-div =3D <16>; + clock-mult =3D <1>; + }; + can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_can_ser>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + i2c_ser_clk: i2c-ser-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_vdi>; + #clock-cells =3D <0>; + clock-div =3D <20>; + clock-mult =3D <1>; + }; +/* PLL_PER derivatives */ + occ_periph: occ-periph { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_per>; + #clock-cells =3D <0>; + clock-div =3D <16>; + clock-mult =3D <1>; + }; + periph_clk: periph-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + can_clk: can-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + spi_clk: spi-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + uart_clk: uart-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + }; + i2c_clk: i2c-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + clock-output-names =3D "i2c_clk"; + }; + timer_clk: timer-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + clock-output-names =3D "timer_clk"; + }; + gpio_clk: gpio-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_periph>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + clock-output-names =3D "gpio_clk"; + }; + emmc_sys_clk: emmc-sys-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_per>; + #clock-cells =3D <0>; + clock-div =3D <10>; + clock-mult =3D <1>; + clock-output-names =3D "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf-ctrl-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_per>; + #clock-cells =3D <0>; + clock-div =3D <4>; + clock-mult =3D <1>; + clock-output-names =3D "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ-mjpeg-core { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_per>; + #clock-cells =3D <0>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "occ_mjpeg_core"; + }; + hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_mjpeg_core>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + clock-output-names =3D "hsm_clk"; + }; + mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ + compatible =3D "fixed-factor-clock"; + clocks =3D <&occ_mjpeg_core>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <1>; + clock-output-names =3D "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu-a-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_per>; + #clock-cells =3D <0>; + clock-div =3D <20>; + clock-mult =3D <1>; + clock-output-names =3D "fcmu_a_clk"; + }; + occ_pci_sys: occ-pci-sys { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll_per>; + #clock-cells =3D <0>; + clock-div =3D <8>; + clock-mult =3D <1>; + clock-output-names =3D "occ_pci_sys"; + }; + pclk: pclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; /* 250MHz */ + }; + tsu_clk: tsu-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; /* 125MHz */ + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mo= bileye/eyeq5.dtsi new file mode 100644 index 0000000000000..2968c467a0552 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* +* Copyright 2023 Mobileye Vision Technologies Ltd. +*/ + +#include + +/memreserve/ 0x40000000 0xc0000000; /* DDR32 */ +/memreserve/ 0x08000000 0x08000000; /* DDR_LOW */ + +#include "eyeq5-fixed-clocks.dtsi" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu@0 { + device_type =3D "cpu"; + compatible =3D "img,i6500"; + reg =3D <0>; + clocks =3D <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg =3D <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg =3D <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0-msi@806000000 { + reg =3D <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1-msi@806100000 { + reg =3D <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini-coredump0@806200000 { + reg =3D <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the-mhm-reserved-0@0 { + reg =3D <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + }; + + cpu_intc: interrupt-controller { + compatible =3D "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + soc: soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + compatible =3D "simple-bus"; + + uart0: serial@800000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0 0x800000 0x0 0x1000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clocks =3D <&uart_clk>, <&occ_periph>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0 0x900000 0x0 0x1000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clocks =3D <&uart_clk>, <&occ_periph>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0 0xa00000 0x0 0x1000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clocks =3D <&uart_clk>, <&occ_periph>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + olb: olb@e00000 { + compatible =3D "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg =3D <0 0xe00000 0x0 0x400>; + reg-io-width =3D <4>; + }; + + gic: interrupt-controller@140000 { + compatible =3D "mti,gic"; + reg =3D <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells =3D <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent =3D <&cpu_intc>; + + timer { + compatible =3D "mti,gic-timer"; + interrupts =3D ; + clocks =3D <&core0_clk>; + }; + }; + }; +}; + --=20 2.42.0