From nobody Tue Dec 16 20:32:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C7DBC4167B for ; Fri, 8 Dec 2023 09:48:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573476AbjLHJsR (ORCPT ); Fri, 8 Dec 2023 04:48:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573452AbjLHJsG (ORCPT ); Fri, 8 Dec 2023 04:48:06 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40D5810CA; Fri, 8 Dec 2023 01:48:11 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3B89ljlW7802618, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3B89ljlW7802618 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 8 Dec 2023 17:47:45 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Fri, 8 Dec 2023 17:47:46 +0800 Received: from RTDOMAIN (172.21.210.160) by RTEXMBS04.realtek.com.tw (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Fri, 8 Dec 2023 17:47:45 +0800 From: Justin Lai To: CC: , , , , , , , , Justin Lai Subject: [PATCH net-next v14 03/13] rtase: Implement the rtase_down function Date: Fri, 8 Dec 2023 17:47:23 +0800 Message-ID: <20231208094733.1671296-4-justinlai0215@realtek.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208094733.1671296-1-justinlai0215@realtek.com> References: <20231208094733.1671296-1-justinlai0215@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.210.160] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS04.realtek.com.tw (172.21.6.97) X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the rtase_down function to disable hardware setting and interrupt and clear descriptor ring. Signed-off-by: Justin Lai --- .../net/ethernet/realtek/rtase/rtase_main.c | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/drivers/net/ethernet/realtek/rtase/rtase_main.c b/drivers/net/= ethernet/realtek/rtase/rtase_main.c index 78a21a9877c4..a4fe0e0ca721 100644 --- a/drivers/net/ethernet/realtek/rtase/rtase_main.c +++ b/drivers/net/ethernet/realtek/rtase/rtase_main.c @@ -189,6 +189,57 @@ static void rtase_free_desc(struct rtase_private *tp) } } =20 +static void rtase_unmap_tx_skb(struct pci_dev *pdev, u32 len, + struct tx_desc *desc) +{ + dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len, + DMA_TO_DEVICE); + desc->opts1 =3D cpu_to_le32(RTK_OPTS1_DEBUG_VALUE); + desc->opts2 =3D 0x00; + desc->addr =3D cpu_to_le64(RTK_MAGIC_NUMBER); +} + +static void rtase_tx_clear_range(struct rtase_ring *ring, u32 start, u32 n) +{ + const struct rtase_private *tp =3D ring->ivec->tp; + struct tx_desc *desc_base =3D ring->desc; + struct net_device *dev =3D tp->dev; + u32 i; + + for (i =3D 0; i < n; i++) { + u32 entry =3D (start + i) % NUM_DESC; + struct tx_desc *desc =3D desc_base + entry; + u32 len =3D ring->mis.len[entry]; + struct sk_buff *skb; + + if (len =3D=3D 0) + continue; + + rtase_unmap_tx_skb(tp->pdev, len, desc); + ring->mis.len[entry] =3D 0; + skb =3D ring->skbuff[entry]; + if (!skb) + continue; + + dev->stats.tx_dropped++; + dev_kfree_skb_any(skb); + ring->skbuff[entry] =3D NULL; + } +} + +static void rtase_tx_clear(struct rtase_private *tp) +{ + struct rtase_ring *ring; + u16 i; + + for (i =3D 0; i < tp->func_tx_queue_num; i++) { + ring =3D &tp->tx_ring[i]; + rtase_tx_clear_range(ring, ring->dirty_idx, NUM_DESC); + ring->cur_idx =3D 0; + ring->dirty_idx =3D 0; + } +} + static void rtase_mark_to_asic(union rx_desc *desc, u32 rx_buf_sz) { u32 eor =3D le32_to_cpu(desc->desc_cmd.opts1) & RING_END; @@ -422,6 +473,77 @@ static void rtase_tally_counter_clear(const struct rta= se_private *tp) rtase_w32(tp, RTASE_DTCCR0, cmd | COUNTER_RESET); } =20 +static void rtase_irq_dis_and_clear(const struct rtase_private *tp) +{ + const struct rtase_int_vector *ivec =3D &tp->int_vector[0]; + u32 val1; + u16 val2; + u8 i; + + rtase_w32(tp, ivec->imr_addr, 0); + val1 =3D rtase_r32(tp, ivec->isr_addr); + rtase_w32(tp, ivec->isr_addr, val1); + + for (i =3D 1; i < tp->int_nums; i++) { + ivec =3D &tp->int_vector[i]; + rtase_w16(tp, ivec->imr_addr, 0); + val2 =3D rtase_r16(tp, ivec->isr_addr); + rtase_w16(tp, ivec->isr_addr, val2); + } +} + +static void rtase_poll_timeout(const struct rtase_private *tp, u32 cond, + u32 sleep_us, u64 timeout_us, u16 reg) +{ + int err; + u8 val; + + err =3D read_poll_timeout(rtase_r8, val, val & cond, sleep_us, timeout_us, + false, tp, reg); + + if (err =3D=3D -ETIMEDOUT) + netdev_err(tp->dev, "poll reg 0x00%x timeout\n", reg); +} + +static void rtase_nic_reset(const struct net_device *dev) +{ + const struct rtase_private *tp =3D netdev_priv(dev); + u16 rx_config; + u8 val; + + rx_config =3D rtase_r16(tp, RTASE_RX_CONFIG_0); + rtase_w16(tp, RTASE_RX_CONFIG_0, rx_config & ~ACCEPT_MASK); + + val =3D rtase_r8(tp, RTASE_MISC); + rtase_w8(tp, RTASE_MISC, val | RX_DV_GATE_EN); + + val =3D rtase_r8(tp, RTASE_CHIP_CMD); + rtase_w8(tp, RTASE_CHIP_CMD, val | STOP_REQ); + mdelay(2); + + rtase_poll_timeout(tp, STOP_REQ_DONE, 100, 150000, RTASE_CHIP_CMD); + + rtase_poll_timeout(tp, TX_FIFO_EMPTY, 100, 100000, RTASE_FIFOR); + + rtase_poll_timeout(tp, RX_FIFO_EMPTY, 100, 100000, RTASE_FIFOR); + + val =3D rtase_r8(tp, RTASE_CHIP_CMD); + rtase_w8(tp, RTASE_CHIP_CMD, val & ~(TE | RE)); + val =3D rtase_r8(tp, RTASE_CHIP_CMD); + rtase_w8(tp, RTASE_CHIP_CMD, val & ~STOP_REQ); + + rtase_w16(tp, RTASE_RX_CONFIG_0, rx_config); +} + +static void rtase_hw_reset(const struct net_device *dev) +{ + const struct rtase_private *tp =3D netdev_priv(dev); + + rtase_irq_dis_and_clear(tp); + + rtase_nic_reset(dev); +} + static void rtase_nic_enable(const struct net_device *dev) { const struct rtase_private *tp =3D netdev_priv(dev); @@ -527,6 +649,33 @@ static int rtase_open(struct net_device *dev) return ret; } =20 +static void rtase_down(struct net_device *dev) +{ + struct rtase_private *tp =3D netdev_priv(dev); + struct rtase_int_vector *ivec; + u32 i; + + netif_stop_queue(dev); + + /* give a racing hard_start_xmit a few cycles to complete */ + synchronize_rcu(); + + netif_carrier_off(dev); + + for (i =3D 0; i < tp->int_nums; i++) { + ivec =3D &tp->int_vector[i]; + synchronize_irq(ivec->irq); + /* wait for any pending NAPI task to complete */ + napi_disable(&ivec->napi); + } + + rtase_hw_reset(dev); + + rtase_tx_clear(tp); + + rtase_rx_clear(tp); +} + static int rtase_close(struct net_device *dev) { struct rtase_private *tp =3D netdev_priv(dev); --=20 2.34.1