From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFB8AC4167B for ; Fri, 8 Dec 2023 05:55:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233256AbjLHFzD (ORCPT ); Fri, 8 Dec 2023 00:55:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232909AbjLHFzA (ORCPT ); Fri, 8 Dec 2023 00:55:00 -0500 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B29AC1727 for ; Thu, 7 Dec 2023 21:55:04 -0800 (PST) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6ce33234fd7so1136192b3a.0 for ; Thu, 07 Dec 2023 21:55:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1702014904; x=1702619704; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cT/f+zG+eBk9GDNM3PRDRS7FWs4vWVwDUJpda1v2enk=; b=Dk8xWHfZUEGYbcq4rBFQOt5NQX1WON5x0U03CMOa1gXwmiOHsQ1+cjsCrw58iIsRMg IKnXNYpyf6ARFQkPvi9k/8Xcmp4eSXf83/eKRPBJTAxyuhx/Jk1eKduJ6mcQ3OH6cCP8 eFi6iM35kXFxXlsKMAWkmXDWbgXm9p7UYUZE7Ha8n4gWb7q/ZSvuJthn8sojYk38IOMK 9ybjvw9uSUar+rl1fer5qNtkEPSVoKyeidlKAPogOFxNC9JgTf81nyLr1Wg1SR1AOtas xVW1CVKp2r6T916J6rhLHiclSqifFTC5LJJ0Z0NZpMFHTIZzFxVnBRMhcs0HmWRvpAyB ynew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702014904; x=1702619704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cT/f+zG+eBk9GDNM3PRDRS7FWs4vWVwDUJpda1v2enk=; b=HMnwudvKPgSct+iSm5r6xuCgajztDuhOB6dZ3b2CyGifmjPWuQeQegQ/ZP8fD5p6XG t84dlLr4B3jMXI/lbSO2RXRLy3RzMoo/PBAwyOzbapsBFTg0DJuyglYG5XmRBbexlRTQ Cm6DvqXLKG20NFR7bntNpcdgR1WsjmmeFvSL+inMkJlAJ5AjB7G56MXDZnLOqhFYIGo0 pDsaUl12+XL9xpZClHERcJ9CqmMqTtBrRXXCy7GgvpfUcPYrEH7HDjeQ2hCY/CC5dHjY TqQ+Hw0lIA18Zq++SK+XLsTa/vmiWwGkwmU5RBpH8NJFnmiOMLcla22Nt8VEPnd370vk LLYQ== X-Gm-Message-State: AOJu0YyH5T3Efsr8K7MAEGGeG0jYaXyh3zJBp/i7ainyWanUwo4qoDaf LhOWnYTggcoEHwiCgBBKEWYq+g== X-Google-Smtp-Source: AGHT+IHjHZOPQupU2gBIY1LJy6ZLE2Spe4muScdMLjHj9er/qEsoCLB+Of3eLXhwYzBMH5NUihe96w== X-Received: by 2002:a05:6a20:160a:b0:190:14d9:4797 with SMTP id l10-20020a056a20160a00b0019014d94797mr1355279pzj.4.1702014904099; Thu, 07 Dec 2023 21:55:04 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:03 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 01/12] arch: Add ARCH_HAS_KERNEL_FPU_SUPPORT Date: Thu, 7 Dec 2023 21:54:31 -0800 Message-ID: <20231208055501.2916202-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Several architectures provide an API to enable the FPU and run floating-point SIMD code in kernel space. However, the function names, header locations, and semantics are inconsistent across architectures, and FPU support may be gated behind other Kconfig options. Provide a standard way for architectures to declare that kernel space FPU support is available. Architectures selecting this option must implement what is currently the most common API (kernel_fpu_begin() and kernel_fpu_end(), plus a new function kernel_fpu_available()) and provide the appropriate CFLAGS for compiling floating-point C code. Suggested-by: Christoph Hellwig Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- Makefile | 4 ++++ arch/Kconfig | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/Makefile b/Makefile index 511b5616aa41..e65c186cf2c9 100644 --- a/Makefile +++ b/Makefile @@ -969,6 +969,10 @@ KBUILD_CFLAGS +=3D $(CC_FLAGS_CFI) export CC_FLAGS_CFI endif =20 +# Architectures can define flags to add/remove for floating-point support +export CC_FLAGS_FPU +export CC_FLAGS_NO_FPU + ifneq ($(CONFIG_FUNCTION_ALIGNMENT),0) KBUILD_CFLAGS +=3D -falign-functions=3D$(CONFIG_FUNCTION_ALIGNMENT) endif diff --git a/arch/Kconfig b/arch/Kconfig index f4b210ab0612..6df834e18e9c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1478,6 +1478,15 @@ config ARCH_HAS_NONLEAF_PMD_YOUNG address translations. Page table walkers that clear the accessed bit may use this capability to reduce their search space. =20 +config ARCH_HAS_KERNEL_FPU_SUPPORT + bool + help + An architecture should select this option if it supports running + floating-point code in kernel space. It must export the functions + kernel_fpu_available(), kernel_fpu_begin(), and kernel_fpu_end() from + , and define CC_FLAGS_FPU and/or CC_FLAGS_NO_FPU as + necessary in its Makefile. + source "kernel/gcov/Kconfig" =20 source "scripts/gcc-plugins/Kconfig" --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51143C4167B for ; Fri, 8 Dec 2023 05:55:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573210AbjLHFzF (ORCPT ); Fri, 8 Dec 2023 00:55:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233153AbjLHFzA (ORCPT ); Fri, 8 Dec 2023 00:55:00 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8115172B for ; Thu, 7 Dec 2023 21:55:05 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1d098b87eeeso15770225ad.0 for ; Thu, 07 Dec 2023 21:55:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1702014905; x=1702619705; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9S9qeMKPrbOjny9ys0DNZnwzZdal5DwwFbQdO5IaRKs=; b=JmSewdVoGFeZo1lHvmaUjEUWED6zUvdSOdnZKKiVDvRmaKzwFw1wS3fNMK7qQfsq89 PhA5q2a0ux/z0wXFMvjO7gjdZ35qeHz4Duaf5bVDnGnvmGR3CZIwtD5FeqXMT58pZ0F/ mot7nAJQFljqLP7pBFPOkpOAD9nFJC4Vl9bY6oxK9dVTmPoIhkCvSNy3/nouXQdk/5U3 tuDppz4hALl7NJZe/7VyXTTbQX3cHLy98yaDSABf2TBxUhESkrWJXpQ4WV3W66ZI+X7G 7Ky8Q6GeOOrqjWcQ+2lCrA1bNmAIO66T79pWGg2HdA6+u92QngLmnHfwppUr0QM8hj+t K7gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702014905; x=1702619705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9S9qeMKPrbOjny9ys0DNZnwzZdal5DwwFbQdO5IaRKs=; b=T3kPCaB4TydRVSOpc8bogYTqyY7XOFQ/D4aCEa8pYEUX5L0tD+CbbdqhX8jsOp0rFh j28n9I3XDrF7iloIdhBPEdM+PDDVcuNAWuEmqiy+JEeJ1AznLj0NOP2OKfBL11wBFeCl I1xgTNCoAnjO0+yA6S+C/JutXiXC9encxOEm8ZXwz+r64Wn6DyOjNzozEaMXH0+wSm/6 5CmGv2PW3DSslXSAPYAFPJ5UjX1n6hkei2MrRDDcpQNe4FgsI7AWiPS66K18z5vWRTY+ D+6BQ11YDyIoU0JeWW+A1FffgTnxtpaLZlQaUx711LKh8stF3tym5WEQPbHg0M3vjuMo wjTg== X-Gm-Message-State: AOJu0YzHM6dc8CCMMww+FkTRwAj3hppa71YhOa4BDj2N5naui+INhORf Lze0nGIYwVA2+WzQW3d6GMIaUg== X-Google-Smtp-Source: AGHT+IHfVmDuQcwcTNkJBCCNyd1od5dj0sgf6cJP7ZkJkjT+CFkpOEIDhByDVUVjY+z9LFISOIDfEQ== X-Received: by 2002:a17:902:6844:b0:1cf:b190:ea07 with SMTP id f4-20020a170902684400b001cfb190ea07mr2955137pln.21.1702014905389; Thu, 07 Dec 2023 21:55:05 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:05 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 02/12] ARM: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Date: Thu, 7 Dec 2023 21:54:32 -0800 Message-ID: <20231208055501.2916202-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ARM provides an equivalent to the common kernel-mode FPU API, but in a different header and using different function names. Add a wrapper header, and export CFLAGS adjustments as found in lib/raid6/Makefile. Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- arch/arm/Kconfig | 1 + arch/arm/Makefile | 7 +++++++ arch/arm/include/asm/fpu.h | 17 +++++++++++++++++ 3 files changed, 25 insertions(+) create mode 100644 arch/arm/include/asm/fpu.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f8567e95f98b..92e21a4a2903 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -14,6 +14,7 @@ config ARM select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_KEEPINITRD select ARCH_HAS_KCOV + select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PTE_SPECIAL if ARM_LPAE diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5ba42f69f8ce..1dd860dba5f5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -130,6 +130,13 @@ endif # Accept old syntax despite ".syntax unified" AFLAGS_NOWARN :=3D$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(co= mma)-W) =20 +# The GCC option -ffreestanding is required in order to compile code conta= ining +# ARM/NEON intrinsics in a non C99-compliant environment (such as the kern= el) +CC_FLAGS_FPU :=3D -ffreestanding +# Enable +CC_FLAGS_FPU +=3D -isystem $(shell $(CC) -print-file-name=3Dinclude) +CC_FLAGS_FPU +=3D -march=3Darmv7-a -mfloat-abi=3Dsoftfp -mfpu=3Dneon + ifeq ($(CONFIG_THUMB2_KERNEL),y) CFLAGS_ISA :=3D-Wa,-mimplicit-it=3Dalways $(AFLAGS_NOWARN) AFLAGS_ISA :=3D$(CFLAGS_ISA) -Wa$(comma)-mthumb diff --git a/arch/arm/include/asm/fpu.h b/arch/arm/include/asm/fpu.h new file mode 100644 index 000000000000..d01ca06e700a --- /dev/null +++ b/arch/arm/include/asm/fpu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/arch/arm/include/asm/fpu.h + * + * Copyright (C) 2023 SiFive + */ + +#ifndef __ASM_FPU_H +#define __ASM_FPU_H + +#include + +#define kernel_fpu_available() cpu_has_neon() +#define kernel_fpu_begin() kernel_neon_begin() +#define kernel_fpu_end() kernel_neon_end() + +#endif /* ! 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Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- arch/arm/lib/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 650404be6768..0ca5aae1bcc3 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -40,8 +40,7 @@ $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S =20 ifeq ($(CONFIG_KERNEL_MODE_NEON),y) - NEON_FLAGS :=3D -march=3Darmv7-a -mfloat-abi=3Dsoftfp -mfpu=3Dneon - CFLAGS_xor-neon.o +=3D $(NEON_FLAGS) + CFLAGS_xor-neon.o +=3D $(CC_FLAGS_FPU) obj-$(CONFIG_XOR_BLOCKS) +=3D xor-neon.o endif =20 --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D89EC4167B for ; Fri, 8 Dec 2023 05:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573235AbjLHFzP (ORCPT ); Fri, 8 Dec 2023 00:55:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233240AbjLHFzD (ORCPT ); Fri, 8 Dec 2023 00:55:03 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50E82171D for ; Thu, 7 Dec 2023 21:55:08 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1d0bcc0c313so12829145ad.3 for ; Thu, 07 Dec 2023 21:55:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1702014908; x=1702619708; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y10I6kBvaoBdzCYCMFFIBpivZ4OdHpoiZkoWcSRPSMo=; b=LsZ+1abePke2lWjvnjGEMnRKRFedjn2235vw5scbYl+tO/bO6ZKjEikpE/NVfV2rQN wKhxHdX8X9kN7Tg5UjdnKKJotveENdlKlUExf8lqiyTUsdV/Th2SLK9K2mhQVqOkjh3+ AVkIKXkrYFUUH1L7JT9ttyLOOFllpdEdAJZxKuwW4mWvq+OkT/vG+a0LpifJGKbhmMpA ktpJwCfL+mWYRX0+a0Mj6pMhEcU/yE6vEO1IrQnlBEnG/UMQCr8KFlO56qA5mXKGnK+U l1G1dzqzIRN2hV20Fro2IZLdtgtq9crtLriu8h3Fa4Xqlfl45rhJPr8sRyXrkV+A+X97 BZOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702014908; x=1702619708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y10I6kBvaoBdzCYCMFFIBpivZ4OdHpoiZkoWcSRPSMo=; b=k4Fahvrr8ZfwCcE+7792eeD7Dd00h29Go4TJv94NDYKlWy6GXdfw0IIafnkAvbwK6A Zen/HqvJo222q89muB3OHw3TJ3EWrPBKoCjCSjw+hXbmlZqzXjKyuYsKRddGaw0lxPBT MI2QCcKQ2m4OkDMhJvZBddcrM4ZTqhH2l1Xy2tCOAgmmlakm4bsOVDZuO+qshGWTPYZB TB9BLawlnUpnaPnzCNyJr/9yHacu9KPl62LGi7GPdcXYkhRfGbS3mL18mWUAcXmpT6DI +HbpWtg5/waOj8TpwVoEpM+QsdC7kufiRZWy1lz5MgNbh6Fs78dMOITYDt0HNIU6RciO Pbww== X-Gm-Message-State: AOJu0Yzwpmh8JOM1bZ1UOmYaM+W9PZSELYyy8YoY6JUWobDwMu7maXpM r49+zrWIrlwysyI8WSt6TNTkIQ+iT9qff+H/488= X-Google-Smtp-Source: AGHT+IEV61WWeWMu7V3217Zpahk/hLH31IwX3YH3+NDaZQD5K6JU/sf2eERQjPEIU9FeQqZ//wlz9w== X-Received: by 2002:a17:903:983:b0:1d0:bba1:57c1 with SMTP id mb3-20020a170903098300b001d0bba157c1mr3658032plb.78.1702014907827; Thu, 07 Dec 2023 21:55:07 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:07 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 04/12] arm64: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Date: Thu, 7 Dec 2023 21:54:34 -0800 Message-ID: <20231208055501.2916202-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" arm64 provides an equivalent to the common kernel-mode FPU API, but in a different header and using different function names. Add a wrapper header, and export CFLAGS adjustments as found in lib/raid6/Makefile. Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- arch/arm64/Kconfig | 1 + arch/arm64/Makefile | 9 ++++++++- arch/arm64/include/asm/fpu.h | 17 +++++++++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/fpu.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 7b071a00425d..485ac389ac11 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -30,6 +30,7 @@ config ARM64 select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV + select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON select ARCH_HAS_KEEPINITRD select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 9a2d3723cd0f..4a65f24c7998 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -36,7 +36,14 @@ ifeq ($(CONFIG_BROKEN_GAS_INST),y) $(warning Detected assembler with broken .inst; disassembly will be unreli= able) endif =20 -KBUILD_CFLAGS +=3D -mgeneral-regs-only \ +# The GCC option -ffreestanding is required in order to compile code conta= ining +# ARM/NEON intrinsics in a non C99-compliant environment (such as the kern= el) +CC_FLAGS_FPU :=3D -ffreestanding +# Enable +CC_FLAGS_FPU +=3D -isystem $(shell $(CC) -print-file-name=3Dinclude) +CC_FLAGS_NO_FPU :=3D -mgeneral-regs-only + +KBUILD_CFLAGS +=3D $(CC_FLAGS_NO_FPU) \ $(compat_vdso) $(cc_has_k_constraint) KBUILD_CFLAGS +=3D $(call cc-disable-warning, psabi) KBUILD_AFLAGS +=3D $(compat_vdso) diff --git a/arch/arm64/include/asm/fpu.h b/arch/arm64/include/asm/fpu.h new file mode 100644 index 000000000000..664c0a192ab1 --- /dev/null +++ b/arch/arm64/include/asm/fpu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/arch/arm64/include/asm/fpu.h + * + * Copyright (C) 2023 SiFive + */ + +#ifndef __ASM_FPU_H +#define __ASM_FPU_H + +#include + +#define kernel_fpu_available() cpu_has_neon() +#define kernel_fpu_begin() kernel_neon_begin() +#define kernel_fpu_end() kernel_neon_end() + +#endif /* ! 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Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- lib/raid6/Makefile | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile index 1c5420ff254e..309fea97efc6 100644 --- a/lib/raid6/Makefile +++ b/lib/raid6/Makefile @@ -33,25 +33,6 @@ CFLAGS_REMOVE_vpermxor8.o +=3D -msoft-float endif endif =20 -# The GCC option -ffreestanding is required in order to compile code conta= ining -# ARM/NEON intrinsics in a non C99-compliant environment (such as the kern= el) -ifeq ($(CONFIG_KERNEL_MODE_NEON),y) -NEON_FLAGS :=3D -ffreestanding -# Enable -NEON_FLAGS +=3D -isystem $(shell $(CC) -print-file-name=3Dinclude) -ifeq ($(ARCH),arm) -NEON_FLAGS +=3D -march=3Darmv7-a -mfloat-abi=3Dsoftfp -mfpu=3Dneon -endif -CFLAGS_recov_neon_inner.o +=3D $(NEON_FLAGS) -ifeq ($(ARCH),arm64) -CFLAGS_REMOVE_recov_neon_inner.o +=3D -mgeneral-regs-only -CFLAGS_REMOVE_neon1.o +=3D -mgeneral-regs-only -CFLAGS_REMOVE_neon2.o +=3D -mgeneral-regs-only -CFLAGS_REMOVE_neon4.o +=3D -mgeneral-regs-only -CFLAGS_REMOVE_neon8.o +=3D -mgeneral-regs-only -endif -endif - quiet_cmd_unroll =3D UNROLL $@ cmd_unroll =3D $(AWK) -v N=3D$* -f $(srctree)/$(src)/unroll.awk < $<= > $@ =20 @@ -75,10 +56,14 @@ targets +=3D vpermxor1.c vpermxor2.c vpermxor4.c vpermx= or8.c $(obj)/vpermxor%.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE $(call if_changed,unroll) =20 -CFLAGS_neon1.o +=3D $(NEON_FLAGS) -CFLAGS_neon2.o +=3D $(NEON_FLAGS) -CFLAGS_neon4.o +=3D $(NEON_FLAGS) -CFLAGS_neon8.o +=3D $(NEON_FLAGS) +CFLAGS_neon1.o +=3D $(CC_FLAGS_FPU) +CFLAGS_neon2.o +=3D $(CC_FLAGS_FPU) +CFLAGS_neon4.o +=3D $(CC_FLAGS_FPU) +CFLAGS_neon8.o +=3D $(CC_FLAGS_FPU) +CFLAGS_REMOVE_neon1.o +=3D $(CC_FLAGS_NO_FPU) +CFLAGS_REMOVE_neon2.o +=3D $(CC_FLAGS_NO_FPU) +CFLAGS_REMOVE_neon4.o +=3D $(CC_FLAGS_NO_FPU) +CFLAGS_REMOVE_neon8.o +=3D $(CC_FLAGS_NO_FPU) targets +=3D neon1.c neon2.c neon4.c neon8.c $(obj)/neon%.c: $(src)/neon.uc $(src)/unroll.awk FORCE $(call if_changed,unroll) --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BD89C4167B for ; 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Thu, 07 Dec 2023 21:55:10 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:09 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 06/12] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Date: Thu, 7 Dec 2023 21:54:36 -0800 Message-ID: <20231208055501.2916202-7-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" LoongArch already provides kernel_fpu_begin() and kernel_fpu_end() in asm/fpu.h, so it only needs to add kernel_fpu_available() and export the CFLAGS adjustments. Signed-off-by: Samuel Holland Acked-by: WANG Xuerui Reviewed-by: Christoph Hellwig --- arch/loongarch/Kconfig | 1 + arch/loongarch/Makefile | 5 ++++- arch/loongarch/include/asm/fpu.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index ee123820a476..65d4475565b8 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -15,6 +15,7 @@ config LOONGARCH select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_KCOV + select ARCH_HAS_KERNEL_FPU_SUPPORT if CPU_HAS_FPU select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PTE_SPECIAL diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile index 204b94b2e6aa..f5c4f7e921db 100644 --- a/arch/loongarch/Makefile +++ b/arch/loongarch/Makefile @@ -25,6 +25,9 @@ endif 32bit-emul =3D elf32loongarch 64bit-emul =3D elf64loongarch =20 +CC_FLAGS_FPU :=3D -mfpu=3D64 +CC_FLAGS_NO_FPU :=3D -msoft-float + ifdef CONFIG_DYNAMIC_FTRACE KBUILD_CPPFLAGS +=3D -DCC_USING_PATCHABLE_FUNCTION_ENTRY CC_FLAGS_FTRACE :=3D -fpatchable-function-entry=3D2 @@ -46,7 +49,7 @@ ld-emul =3D $(64bit-emul) cflags-y +=3D -mabi=3Dlp64s endif =20 -cflags-y +=3D -pipe -msoft-float +cflags-y +=3D -pipe $(CC_FLAGS_NO_FPU) LDFLAGS_vmlinux +=3D -static -n -nostdlib =20 # When the assembler supports explicit relocation hint, we must use it. diff --git a/arch/loongarch/include/asm/fpu.h b/arch/loongarch/include/asm/= fpu.h index c2d8962fda00..3177674228f8 100644 --- a/arch/loongarch/include/asm/fpu.h +++ b/arch/loongarch/include/asm/fpu.h @@ -21,6 +21,7 @@ =20 struct sigcontext; =20 +#define kernel_fpu_available() cpu_has_fpu extern void kernel_fpu_begin(void); extern void kernel_fpu_end(void); =20 --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24EFCC4167B for ; Fri, 8 Dec 2023 05:55:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235691AbjLHFzc (ORCPT ); Fri, 8 Dec 2023 00:55:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573214AbjLHFzH (ORCPT ); Fri, 8 Dec 2023 00:55:07 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A1F6172B for ; Thu, 7 Dec 2023 21:55:12 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1d1e1edb10bso15914445ad.1 for ; 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charset="utf-8" PowerPC provides an equivalent to the common kernel-mode FPU API, but in a different header and using different function names. The PowerPC API also requires a non-preemptible context. Add a wrapper header, and export the CFLAGS adjustments. Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- arch/powerpc/Kconfig | 1 + arch/powerpc/Makefile | 5 ++++- arch/powerpc/include/asm/fpu.h | 28 ++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/include/asm/fpu.h diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 6f105ee4f3cf..e96cb5b7c571 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -137,6 +137,7 @@ config PPC select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_HUGEPD if HUGETLB_PAGE select ARCH_HAS_KCOV + select ARCH_HAS_KERNEL_FPU_SUPPORT if PPC_FPU select ARCH_HAS_MEMBARRIER_CALLBACKS select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_MEMREMAP_COMPAT_ALIGN if PPC_64S_HASH_MMU diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index f19dbaa1d541..2d5f21baf6ff 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -142,6 +142,9 @@ CFLAGS-$(CONFIG_PPC32) +=3D $(call cc-option, $(MULTIPL= EWORD)) =20 CFLAGS-$(CONFIG_PPC32) +=3D $(call cc-option,-mno-readonly-in-sdata) =20 +CC_FLAGS_FPU :=3D $(call cc-option,-mhard-float) +CC_FLAGS_NO_FPU +=3D $(call cc-option,-msoft-float) + ifdef CONFIG_FUNCTION_TRACER ifdef CONFIG_ARCH_USING_PATCHABLE_FUNCTION_ENTRY KBUILD_CPPFLAGS +=3D -DCC_USING_PATCHABLE_FUNCTION_ENTRY @@ -163,7 +166,7 @@ asinstr :=3D $(call as-instr,lis 9$(comma)foo@high,-DHA= VE_AS_ATHIGH=3D1) =20 KBUILD_CPPFLAGS +=3D -I $(srctree)/arch/$(ARCH) $(asinstr) KBUILD_AFLAGS +=3D $(AFLAGS-y) -KBUILD_CFLAGS +=3D $(call cc-option,-msoft-float) +KBUILD_CFLAGS +=3D $(CC_FLAGS_NO_FPU) KBUILD_CFLAGS +=3D $(CFLAGS-y) CPP =3D $(CC) -E $(KBUILD_CFLAGS) =20 diff --git a/arch/powerpc/include/asm/fpu.h b/arch/powerpc/include/asm/fpu.h new file mode 100644 index 000000000000..ca584e4bc40f --- /dev/null +++ b/arch/powerpc/include/asm/fpu.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 SiFive + */ + +#ifndef _ASM_POWERPC_FPU_H +#define _ASM_POWERPC_FPU_H + +#include + +#include +#include + +#define kernel_fpu_available() (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + +static inline void kernel_fpu_begin(void) +{ + preempt_disable(); + enable_kernel_fp(); +} + +static inline void kernel_fpu_end(void) +{ + disable_kernel_fp(); + preempt_enable(); +} + +#endif /* ! _ASM_POWERPC_FPU_H */ --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3496C10F09 for ; Fri, 8 Dec 2023 05:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573251AbjLHFz3 (ORCPT ); Fri, 8 Dec 2023 00:55:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573221AbjLHFzI (ORCPT ); Fri, 8 Dec 2023 00:55:08 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35DF41734 for ; Thu, 7 Dec 2023 21:55:13 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1d04d286bc0so13129585ad.3 for ; Thu, 07 Dec 2023 21:55:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1702014912; x=1702619712; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wOdH6gQ2/kSr11qF6anDkZP04y2oGGJwChsMHemqfok=; b=T4LqkHlraVGMzq4C9tWiv8BniomaaUN0FsEXm/RKku0Y5B7y0fPRi1ZQycLzyVP+0T IHZ0KKRXegLktdCL8wQpOigg1hzXyG0Fz4BXDxfWLPffxhqCHZEDogY/hO8fn9bAbLb7 x8VUn4CTv6a21gYTRxMoTNw2CY7FvLNyba3L4EdLCEgxUZSRQGsnS1jKsSHvZh9OQYTG YRmz1T4U+c+XzwmhOgwFh4Io9cyrrIiEUf7TjeDEPiRsKpJ5PyQ5p8GJ1DwZwOWN8Okk PsdM4+U3fxLvx7l35UejxLDN9Xm98edMr5ZgoYi70LOXuLMtEUpdG6zNBUri8pNK+SQM iDkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702014912; x=1702619712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wOdH6gQ2/kSr11qF6anDkZP04y2oGGJwChsMHemqfok=; b=wO6KAk4usKap7zcH1GI30EBEjMdsoTfvLFdcQJVNyn4QUpGr9lDkiBL8dUJ6u1m58k yY0hLr6PChM44Pwk3BEEYz/4gJfWaLnRbgnBt2EJu1X2FlBC91CO3J6HcHhB60CKL8im pXqmEWf6y7xkwSexMS0rALVawY0BgkWH1x6B7suhSVJxyCYz3mntEI3vPBEh5WY+Annd 156oS8hYcULEWXHjftS56K8db76pIZGxxKzLSlGK7sppWdlo/rwQ5CwI60VL+6kdTlXo jh15Cs58U+/aCNM3YL5WaZonQee75xfXpDpBwf9HMJ69+dfNVbjd2VsEoN517zms5KmA y/XQ== X-Gm-Message-State: AOJu0YywjgxLTUzingKrJnJfu1Ie3uLFiqVn2PX903BGsj1HhqYi0KK6 YrFZS4Ik4k4wS0RXFcGp1BFm2iIt/sz5jHgpTh0= X-Google-Smtp-Source: AGHT+IF6KW8xi8WlWkg/kkkF64YaWdAU9w8XTSDFOxfj/W9T6fcHp2B4VJ43fwnOYGHYYluHTLhnIQ== X-Received: by 2002:a17:902:64d0:b0:1d2:eea4:a7d7 with SMTP id y16-20020a17090264d000b001d2eea4a7d7mr180399pli.5.1702014912711; Thu, 07 Dec 2023 21:55:12 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:12 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 08/12] x86: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Date: Thu, 7 Dec 2023 21:54:38 -0800 Message-ID: <20231208055501.2916202-9-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" x86 already provides kernel_fpu_begin() and kernel_fpu_end(), but in a different header. Add a wrapper header, and export the CFLAGS adjustments as found in lib/Makefile. Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- arch/x86/Kconfig | 1 + arch/x86/Makefile | 20 ++++++++++++++++++++ arch/x86/include/asm/fpu.h | 13 +++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 arch/x86/include/asm/fpu.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3762f41bb092..1fe7f2d8d017 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -81,6 +81,7 @@ config X86 select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_KCOV if X86_64 + select ARCH_HAS_KERNEL_FPU_SUPPORT select ARCH_HAS_MEM_ENCRYPT select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 1a068de12a56..71576c8dbe79 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -70,6 +70,26 @@ export BITS KBUILD_CFLAGS +=3D -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx KBUILD_RUSTFLAGS +=3D -Ctarget-feature=3D-sse,-sse2,-sse3,-ssse3,-sse4.1,-= sse4.2,-avx,-avx2 =20 +# +# CFLAGS for compiling floating point code inside the kernel. +# +CC_FLAGS_FPU :=3D -msse -msse2 +ifdef CONFIG_CC_IS_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-bound= ary=3D3 +# (8B stack alignment). +# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D53383 +# +# The "-msse" in the first argument is there so that the +# -mpreferred-stack-boundary=3D3 build error: +# +# -mpreferred-stack-boundary=3D3 is not between 4 and 12 +# +# can be triggered. Otherwise gcc doesn't complain. +CC_FLAGS_FPU +=3D -mhard-float +CC_FLAGS_FPU +=3D $(call cc-option,-msse -mpreferred-stack-boundary=3D3,-m= preferred-stack-boundary=3D4) +endif + ifeq ($(CONFIG_X86_KERNEL_IBT),y) # # Kernel IBT has S_CET.NOTRACK_EN=3D0, as such the compilers must not gene= rate diff --git a/arch/x86/include/asm/fpu.h b/arch/x86/include/asm/fpu.h new file mode 100644 index 000000000000..b2743fe19339 --- /dev/null +++ b/arch/x86/include/asm/fpu.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 SiFive + */ + +#ifndef _ASM_X86_FPU_H +#define _ASM_X86_FPU_H + +#include + +#define kernel_fpu_available() true + +#endif /* ! _ASM_X86_FPU_H */ --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 214A9C4167B for ; Fri, 8 Dec 2023 05:55:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573256AbjLHFzh (ORCPT ); Fri, 8 Dec 2023 00:55:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573226AbjLHFzK (ORCPT ); Fri, 8 Dec 2023 00:55:10 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71CA21721 for ; Thu, 7 Dec 2023 21:55:14 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1cf7a8ab047so12901935ad.1 for ; Thu, 07 Dec 2023 21:55:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1702014914; x=1702619714; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YYvZSY93/xrjeeL5ETwAXbtukKNXxCCQ4+T0woOWU40=; b=AHmyGEfxc3LH7QLB/XcbwdIp1OfktJXk8rSFWe5BEOz3ExHQDJ3iiIGlnZiHfPwkuv VVLQ+cbpSbgDfHoXvxvJoiuwiQA20H/57xjh4HgRx/qp+qAe52IUcntWbwRP3LFmsyG+ 6VMY0aGz1+5pZsupP0QCYDdUkYydQBKkOGaIDJm4E+zlClexqG53Bbo5TAeQqn+yF78t 4rHfIEmiop/8EvTaPKQi51s/nD1JcrpE0xSwAj8OMEWEWuFc4CQBeCfMJF2UILJPLwUE +0zcCHx0gTh1v+9OH0f4a1HpCyjFNJ0VSPiJL46MpuCp/iHSshq/kkFf2oPJuJC/+brZ TSpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702014914; x=1702619714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YYvZSY93/xrjeeL5ETwAXbtukKNXxCCQ4+T0woOWU40=; b=Aq4j2NMNew53qp9VJVjSSapowPm9biq1oR4vfE5YfztTMUtYvanjWVwCYyDIf4WLDC vqChr6eLF4F+fFCiAr7QesDIZpC5rZ5w0tbHL2VnB2pvJYTzmpgY8srZqcuBgQX1IcqJ vWcl0tyb91ilLWXBm1Hn3oSrhBcF6kitUx8iMjJaWmdXnJrcihKQJ9/GTfzyX2/W6gdg DLjPAdKIpkgfwFoFiUWcuPCG36cm2O3anPPo9kC6tAN7la4vFlAHczhaduNPAWbbbzdE ZxUEf11yS3MgKl/kRzbuLc1XSpuF748Wd+cDkhKrQ4BwSQMGtd218eJwqZRVn/nrIkmQ 42aA== X-Gm-Message-State: AOJu0Yywp/FsFTb3mbIrKRBfi6qKiqHBkAC2Q9yuEG2RESzcy4w9/gUU X2M1G/vJh/7avqCjSl+RQEBTFg== X-Google-Smtp-Source: AGHT+IEX6fsur3fhby/cWKLu/7STh1pjdXEZxMWOcghK1shSxSRPNcFQAcmIt0ejFquarrBp9mMVPA== X-Received: by 2002:a17:902:e541:b0:1d0:a084:affd with SMTP id n1-20020a170902e54100b001d0a084affdmr3001010plf.73.1702014913936; Thu, 07 Dec 2023 21:55:13 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:13 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 09/12] riscv: Add support for kernel-mode FPU Date: Thu, 7 Dec 2023 21:54:39 -0800 Message-ID: <20231208055501.2916202-10-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is motivated by the amdgpu DRM driver, which needs floating-point code to support recent hardware. That code is not performance-critical, so only provide a minimal non-preemptible implementation for now. Use a similar trick as ARM to force placing floating-point code in a separate translation unit, so it is not possible for compiler-generated floating-point code to appear outside kernel_fpu_{begin,end}(). Signed-off-by: Samuel Holland --- arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 3 +++ arch/riscv/include/asm/fpu.h | 26 ++++++++++++++++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/kernel_mode_fpu.c | 28 ++++++++++++++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 arch/riscv/include/asm/fpu.h create mode 100644 arch/riscv/kernel/kernel_mode_fpu.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 95a2a06acc6a..cf0967928e6d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,6 +27,7 @@ config RISCV select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV + select ARCH_HAS_KERNEL_FPU_SUPPORT if FPU select ARCH_HAS_MMIOWB select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PMEM_API diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index a74be78678eb..2e719c369210 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -81,6 +81,9 @@ KBUILD_CFLAGS +=3D -march=3D$(shell echo $(riscv-march-y)= | sed -E 's/(rv32ima|rv64i =20 KBUILD_AFLAGS +=3D -march=3D$(riscv-march-y) =20 +# For C code built with floating-point support, exclude V but keep F and D. +CC_FLAGS_FPU :=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv3= 2ima|rv64ima)([^v_]*)v?/\1\2/') + KBUILD_CFLAGS +=3D -mno-save-restore KBUILD_CFLAGS +=3D -DCONFIG_PAGE_OFFSET=3D$(CONFIG_PAGE_OFFSET) =20 diff --git a/arch/riscv/include/asm/fpu.h b/arch/riscv/include/asm/fpu.h new file mode 100644 index 000000000000..8cd027acc015 --- /dev/null +++ b/arch/riscv/include/asm/fpu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 SiFive + */ + +#ifndef _ASM_RISCV_FPU_H +#define _ASM_RISCV_FPU_H + +#include + +#define kernel_fpu_available() has_fpu() + +#ifdef __riscv_f + +#define kernel_fpu_begin() \ + static_assert(false, "floating-point code must use a separate translation= unit") +#define kernel_fpu_end() kernel_fpu_begin() + +#else + +void kernel_fpu_begin(void); +void kernel_fpu_end(void); + +#endif + +#endif /* ! _ASM_RISCV_FPU_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fee22a3d1b53..662c483e338d 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 obj-$(CONFIG_RISCV_MISALIGNED) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o +obj-$(CONFIG_FPU) +=3D kernel_mode_fpu.o obj-$(CONFIG_RISCV_ISA_V) +=3D vector.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o diff --git a/arch/riscv/kernel/kernel_mode_fpu.c b/arch/riscv/kernel/kernel= _mode_fpu.c new file mode 100644 index 000000000000..9b2024cc056b --- /dev/null +++ b/arch/riscv/kernel/kernel_mode_fpu.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 SiFive + */ + +#include +#include + +#include +#include +#include +#include + +void kernel_fpu_begin(void) +{ + preempt_disable(); + fstate_save(current, task_pt_regs(current)); + csr_set(CSR_SSTATUS, SR_FS); +} +EXPORT_SYMBOL_GPL(kernel_fpu_begin); + +void kernel_fpu_end(void) +{ + csr_clear(CSR_SSTATUS, SR_FS); + fstate_restore(current, task_pt_regs(current)); + preempt_enable(); +} +EXPORT_SYMBOL_GPL(kernel_fpu_end); --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E82CC10F04 for ; Fri, 8 Dec 2023 05:56:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573202AbjLHFzx (ORCPT ); Fri, 8 Dec 2023 00:55:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573238AbjLHFzS (ORCPT ); Fri, 8 Dec 2023 00:55:18 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9356171F for ; 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bh=/zgqNM1BLjQpwqOX8AAkpOEPaYmCztUSTZLlWDykd+Y=; b=o9VjQMlvozCY1pS/9xqDap2EDEdCartvJ5u7vtumxOwKOLL0qU0px/8Bo9lh2bRZpR Am3lEyesBqjY2HgDx4+Ij4ncWooW9wWeCk1/nWqI0e3IrCygd1Y9/Je7Qjf4qyHZYyv0 xCa/AiM12JWBMRjEScswtgmPLBOOi+wbnUcSYNkxk+6gt/H9G+sivCe4MWdUuAhHf6ZS aOlYImKKHXVbBwyObHt1bpueLZud7doVWRxvu4Nc1MfuGdbz96MVn8XhW9fYcP36TL8i NfRVOBUciHuNpsNjy1EwdtqUiN7fMfpJmBtJzFOxhqJ6yP/boowCzkfTv1HozozC8im+ tI4A== X-Gm-Message-State: AOJu0YwlJZTX1jRN0WM0qm3tpN00cbAh/72mZhkKqysySs9GzzQu5jLC bHA3xDg3daFYuzBiy48CFUO+jg== X-Google-Smtp-Source: AGHT+IEeohhdRoDbIB76rfeg/hp1f0wvfoQ9mNCmH7fkkS6XWgt0u4/Ycqf6R8fGDv+mLvCYfXsFug== X-Received: by 2002:a17:902:e88a:b0:1d0:68a:4a46 with SMTP id w10-20020a170902e88a00b001d0068a4a46mr4585686plg.3.1702014915181; Thu, 07 Dec 2023 21:55:15 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001ce5b859a59sm786250plp.305.2023.12.07.21.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 21:55:14 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 10/12] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT Date: Thu, 7 Dec 2023 21:54:40 -0800 Message-ID: <20231208055501.2916202-11-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that all previously-supported architectures select ARCH_HAS_KERNEL_FPU_SUPPORT, this code can depend on that symbol instead of the existing list of architectures. It can also take advantage of the common kernel-mode FPU API and method of adjusting CFLAGS. Signed-off-by: Samuel Holland --- drivers/gpu/drm/amd/display/Kconfig | 2 +- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 33 +---------------- drivers/gpu/drm/amd/display/dc/dml/Makefile | 36 ++----------------- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 36 ++----------------- 4 files changed, 6 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/disp= lay/Kconfig index 901d1961b739..5fcd4f778dc3 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -8,7 +8,7 @@ config DRM_AMD_DC depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64 select SND_HDA_COMPONENT if SND_HDA_CORE # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 - select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64= && KERNEL_MODE_NEON && !CC_IS_CLANG)) + select DRM_AMD_DC_FP if ARCH_HAS_KERNEL_FPU_SUPPORT && (!ARM64 || !CC_IS_= CLANG) help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/d= rm/amd/display/amdgpu_dm/dc_fpu.c index 4ae4720535a5..b64f917174ca 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -26,16 +26,7 @@ =20 #include "dc_trace.h" =20 -#if defined(CONFIG_X86) -#include -#elif defined(CONFIG_PPC64) -#include -#include -#elif defined(CONFIG_ARM64) -#include -#elif defined(CONFIG_LOONGARCH) #include -#endif =20 /** * DOC: DC FPU manipulation overview @@ -87,20 +78,9 @@ void dc_fpu_begin(const char *function_name, const int l= ine) WARN_ON_ONCE(!in_task()); preempt_disable(); depth =3D __this_cpu_inc_return(fpu_recursion_depth); - if (depth =3D=3D 1) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) + BUG_ON(!kernel_fpu_available()); kernel_fpu_begin(); -#elif defined(CONFIG_PPC64) - if (cpu_has_feature(CPU_FTR_VSX_COMP)) - enable_kernel_vsx(); - else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) - enable_kernel_altivec(); - else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) - enable_kernel_fp(); -#elif defined(CONFIG_ARM64) - kernel_neon_begin(); -#endif } =20 TRACE_DCN_FPU(true, function_name, line, depth); @@ -122,18 +102,7 @@ void dc_fpu_end(const char *function_name, const int l= ine) =20 depth =3D __this_cpu_dec_return(fpu_recursion_depth); if (depth =3D=3D 0) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) kernel_fpu_end(); -#elif defined(CONFIG_PPC64) - if (cpu_has_feature(CPU_FTR_VSX_COMP)) - disable_kernel_vsx(); - else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) - disable_kernel_altivec(); - else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) - disable_kernel_fp(); -#elif defined(CONFIG_ARM64) - kernel_neon_end(); -#endif } else { WARN_ON_ONCE(depth < 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/= amd/display/dc/dml/Makefile index ea7d60f9a9b4..5aad0f572ba3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -25,40 +25,8 @@ # It provides the general basic services required by other DAL # subcomponents. =20 -ifdef CONFIG_X86 -dml_ccflags-$(CONFIG_CC_IS_GCC) :=3D -mhard-float -dml_ccflags :=3D $(dml_ccflags-y) -msse -endif - -ifdef CONFIG_PPC64 -dml_ccflags :=3D -mhard-float -maltivec -endif - -ifdef CONFIG_ARM64 -dml_rcflags :=3D -mgeneral-regs-only -endif - -ifdef CONFIG_LOONGARCH -dml_ccflags :=3D -mfpu=3D64 -dml_rcflags :=3D -msoft-float -endif - -ifdef CONFIG_CC_IS_GCC -ifneq ($(call gcc-min-version, 70100),y) -IS_OLD_GCC =3D 1 -endif -endif - -ifdef CONFIG_X86 -ifdef IS_OLD_GCC -# Stack alignment mismatch, proceed with caution. -# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-bound= ary=3D3 -# (8B stack alignment). -dml_ccflags +=3D -mpreferred-stack-boundary=3D4 -else -dml_ccflags +=3D -msse2 -endif -endif +dml_ccflags :=3D $(CC_FLAGS_FPU) +dml_rcflags :=3D $(CC_FLAGS_NO_FPU) =20 ifneq ($(CONFIG_FRAME_WARN),0) frame_warn_flag :=3D -Wframe-larger-than=3D2048 diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm= /amd/display/dc/dml2/Makefile index acff3449b8d7..4f6c804a26ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -24,40 +24,8 @@ # # Makefile for dml2. =20 -ifdef CONFIG_X86 -dml2_ccflags-$(CONFIG_CC_IS_GCC) :=3D -mhard-float -dml2_ccflags :=3D $(dml2_ccflags-y) -msse -endif - -ifdef CONFIG_PPC64 -dml2_ccflags :=3D -mhard-float -maltivec -endif - -ifdef CONFIG_ARM64 -dml2_rcflags :=3D -mgeneral-regs-only -endif - -ifdef CONFIG_LOONGARCH -dml2_ccflags :=3D -mfpu=3D64 -dml2_rcflags :=3D -msoft-float -endif - -ifdef CONFIG_CC_IS_GCC -ifeq ($(call cc-ifversion, -lt, 0701, y), y) -IS_OLD_GCC =3D 1 -endif -endif - -ifdef CONFIG_X86 -ifdef IS_OLD_GCC -# Stack alignment mismatch, proceed with caution. -# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-bound= ary=3D3 -# (8B stack alignment). -dml2_ccflags +=3D -mpreferred-stack-boundary=3D4 -else -dml2_ccflags +=3D -msse2 -endif -endif +dml2_ccflags :=3D $(CC_FLAGS_FPU) +dml2_rcflags :=3D $(CC_FLAGS_NO_FPU) =20 ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44D66C4167B for ; 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charset="utf-8" This ensures no compiler-generated floating-point code can appear outside kernel_fpu_{begin,end}() sections, and some architectures enforce this separation. Signed-off-by: Samuel Holland --- lib/Makefile | 3 ++- lib/{test_fpu.c =3D> test_fpu_glue.c} | 32 +------------------------- lib/test_fpu_impl.c | 35 +++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 32 deletions(-) rename lib/{test_fpu.c =3D> test_fpu_glue.c} (71%) create mode 100644 lib/test_fpu_impl.c diff --git a/lib/Makefile b/lib/Makefile index 6b09731d8e61..e7cbd54944a2 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -132,7 +132,8 @@ FPU_CFLAGS +=3D $(call cc-option,-msse -mpreferred-stac= k-boundary=3D3,-mpreferred-st endif =20 obj-$(CONFIG_TEST_FPU) +=3D test_fpu.o -CFLAGS_test_fpu.o +=3D $(FPU_CFLAGS) +test_fpu-y :=3D test_fpu_glue.o test_fpu_impl.o +CFLAGS_test_fpu_impl.o +=3D $(FPU_CFLAGS) =20 obj-$(CONFIG_TEST_LIVEPATCH) +=3D livepatch/ =20 diff --git a/lib/test_fpu.c b/lib/test_fpu_glue.c similarity index 71% rename from lib/test_fpu.c rename to lib/test_fpu_glue.c index e82db19fed84..2761b51117b0 100644 --- a/lib/test_fpu.c +++ b/lib/test_fpu_glue.c @@ -19,37 +19,7 @@ #include #include =20 -static int test_fpu(void) -{ - /* - * This sequence of operations tests that rounding mode is - * to nearest and that denormal numbers are supported. - * Volatile variables are used to avoid compiler optimizing - * the calculations away. - */ - volatile double a, b, c, d, e, f, g; - - a =3D 4.0; - b =3D 1e-15; - c =3D 1e-310; - - /* Sets precision flag */ - d =3D a + b; - - /* Result depends on rounding mode */ - e =3D a + b / 2; - - /* Denormal and very large values */ - f =3D b / c; - - /* Depends on denormal support */ - g =3D a + c * f; - - if (d > a && e > a && g > a) - return 0; - else - return -EINVAL; -} +int test_fpu(void); =20 static int test_fpu_get(void *data, u64 *val) { diff --git a/lib/test_fpu_impl.c b/lib/test_fpu_impl.c new file mode 100644 index 000000000000..2ff01980bc22 --- /dev/null +++ b/lib/test_fpu_impl.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + +int test_fpu(void) +{ + /* + * This sequence of operations tests that rounding mode is + * to nearest and that denormal numbers are supported. + * Volatile variables are used to avoid compiler optimizing + * the calculations away. + */ + volatile double a, b, c, d, e, f, g; + + a =3D 4.0; + b =3D 1e-15; + c =3D 1e-310; + + /* Sets precision flag */ + d =3D a + b; + + /* Result depends on rounding mode */ + e =3D a + b / 2; + + /* Denormal and very large values */ + f =3D b / c; + + /* Depends on denormal support */ + g =3D a + c * f; + + if (d > a && e > a && g > a) + return 0; + else + return -EINVAL; +} --=20 2.42.0 From nobody Tue Dec 16 16:40:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C9E5C4167B for ; Fri, 8 Dec 2023 05:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573266AbjLHFz4 (ORCPT ); Fri, 8 Dec 2023 00:55:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235659AbjLHFz2 (ORCPT ); Fri, 8 Dec 2023 00:55:28 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C87E172D for ; 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Thu, 07 Dec 2023 21:55:17 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 12/12] selftests/fpu: Allow building on other architectures Date: Thu, 7 Dec 2023 21:54:42 -0800 Message-ID: <20231208055501.2916202-13-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231208055501.2916202-1-samuel.holland@sifive.com> References: <20231208055501.2916202-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that ARCH_HAS_KERNEL_FPU_SUPPORT provides a common way to compile and run floating-point code, this test is no longer x86-specific. Signed-off-by: Samuel Holland Reviewed-by: Christoph Hellwig --- lib/Kconfig.debug | 2 +- lib/Makefile | 25 ++----------------------- lib/test_fpu_glue.c | 5 ++++- 3 files changed, 7 insertions(+), 25 deletions(-) diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index cc7d53d9dc01..bbab0b054e09 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -2933,7 +2933,7 @@ config TEST_FREE_PAGES =20 config TEST_FPU tristate "Test floating point operations in kernel space" - depends on X86 && !KCOV_INSTRUMENT_ALL + depends on ARCH_HAS_KERNEL_FPU_SUPPORT && !KCOV_INSTRUMENT_ALL help Enable this option to add /sys/kernel/debug/selftest_helpers/test_fpu which will trigger a sequence of floating point operations. This is used diff --git a/lib/Makefile b/lib/Makefile index e7cbd54944a2..b9f28558c9bd 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -109,31 +109,10 @@ CFLAGS_test_fprobe.o +=3D $(CC_FLAGS_FTRACE) obj-$(CONFIG_FPROBE_SANITY_TEST) +=3D test_fprobe.o obj-$(CONFIG_TEST_OBJPOOL) +=3D test_objpool.o =20 -# -# CFLAGS for compiling floating point code inside the kernel. x86/Makefile= turns -# off the generation of FPU/SSE* instructions for kernel proper but FPU_FL= AGS -# get appended last to CFLAGS and thus override those previous compiler op= tions. -# -FPU_CFLAGS :=3D -msse -msse2 -ifdef CONFIG_CC_IS_GCC -# Stack alignment mismatch, proceed with caution. -# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-bound= ary=3D3 -# (8B stack alignment). -# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D53383 -# -# The "-msse" in the first argument is there so that the -# -mpreferred-stack-boundary=3D3 build error: -# -# -mpreferred-stack-boundary=3D3 is not between 4 and 12 -# -# can be triggered. Otherwise gcc doesn't complain. -FPU_CFLAGS +=3D -mhard-float -FPU_CFLAGS +=3D $(call cc-option,-msse -mpreferred-stack-boundary=3D3,-mpr= eferred-stack-boundary=3D4) -endif - obj-$(CONFIG_TEST_FPU) +=3D test_fpu.o test_fpu-y :=3D test_fpu_glue.o test_fpu_impl.o -CFLAGS_test_fpu_impl.o +=3D $(FPU_CFLAGS) +CFLAGS_test_fpu_impl.o +=3D $(CC_FLAGS_FPU) +CFLAGS_REMOVE_test_fpu_impl.o +=3D $(CC_FLAGS_NO_FPU) =20 obj-$(CONFIG_TEST_LIVEPATCH) +=3D livepatch/ =20 diff --git a/lib/test_fpu_glue.c b/lib/test_fpu_glue.c index 2761b51117b0..2e0b4027a5e3 100644 --- a/lib/test_fpu_glue.c +++ b/lib/test_fpu_glue.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include =20 int test_fpu(void); =20 @@ -38,6 +38,9 @@ static struct dentry *selftest_dir; =20 static int __init test_fpu_init(void) { + if (!kernel_fpu_available()) + return -EINVAL; + selftest_dir =3D debugfs_create_dir("selftest_helpers", NULL); if (!selftest_dir) return -ENOMEM; --=20 2.42.0