From nobody Tue Dec 16 20:11:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAFE5C4167B for ; Thu, 7 Dec 2023 22:14:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1444086AbjLGWOh (ORCPT ); Thu, 7 Dec 2023 17:14:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1444057AbjLGWOb (ORCPT ); Thu, 7 Dec 2023 17:14:31 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55F7B10F9; Thu, 7 Dec 2023 14:14:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701987277; x=1733523277; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+9rjm8/R+ymt6ecjZHbZjfxI3PAzoqkWcm1btj/h204=; b=TdktQAo6+9P5/R+opp1ZtfjcJh40gSU2RQ3JZ0gBfd4K7mXrplykPR86 PGyBJ9Ths6L8fgOXRrrJfKIUL8IJqbpZ9AL1mAjpbG5+XVrdKFZpbRe+A FJyiZVgI72WGTYZ8aR9ReK2udBig37qL9jPzJMGCslKdmMlbS0pxb6WUO Q3pMRcofny9ia8NqwntGqLYJzeeXpbVwmn0rm1xMfoUntp9cOvxlqW0dF EZCu+91cgETZQZ3+dHUGSlfPOyi0YUh0irIpwYYMQjyFVeJQxLvmCU877 FXZ+ampfoDpg/Hy14gh5yaqWavQVFfPvu+FdcVcO3PPwSYI+avixbqfZJ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="1197562" X-IronPort-AV: E=Sophos;i="6.04,258,1695711600"; d="scan'208";a="1197562" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2023 14:14:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="842365245" X-IronPort-AV: E=Sophos;i="6.04,258,1695711600"; d="scan'208";a="842365245" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga004.fm.intel.com with ESMTP; 07 Dec 2023 14:14:34 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 148CD154; Fri, 8 Dec 2023 00:14:33 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v1 1/2] spi: pxa2xx: Use inclusive language Date: Fri, 8 Dec 2023 00:13:39 +0200 Message-ID: <20231207221426.3259806-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231207221426.3259806-1-andriy.shevchenko@linux.intel.com> References: <20231207221426.3259806-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace master/slave by host/peripheral language in the documentation. Signed-off-by: Andy Shevchenko --- Documentation/spi/pxa2xx.rst | 48 ++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/Documentation/spi/pxa2xx.rst b/Documentation/spi/pxa2xx.rst index 04f2a3856c40..b66702724ccf 100644 --- a/Documentation/spi/pxa2xx.rst +++ b/Documentation/spi/pxa2xx.rst @@ -3,13 +3,13 @@ PXA2xx SPI on SSP driver HOWTO =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx -synchronous serial port into an SPI master controller +synchronous serial port into an SPI host controller (see Documentation/spi/spi-summary.rst). The driver has the following feat= ures =20 - Support for any PXA2xx and compatible SSP. - SSP PIO and SSP DMA data transfers. - External and Internal (SSPFRM) chip selects. -- Per slave device (chip) configuration. +- Per peripheral device (chip) configuration. - Full suspend, freeze, resume support. =20 The driver is built around a &struct spi_message FIFO serviced by kernel @@ -17,10 +17,10 @@ thread. The kernel thread, spi_pump_messages(), drives = message FIFO and is responsible for queuing SPI transactions and setting up and launching the DMA or interrupt driven transfers. =20 -Declaring PXA2xx Master Controllers ------------------------------------ -Typically, for a legacy platform, an SPI master is defined in the -arch/.../mach-*/board-*.c as a "platform device". The master configuration +Declaring PXA2xx host controllers +--------------------------------- +Typically, for a legacy platform, an SPI host is defined in the +arch/.../mach-*/board-*.c as a "platform device". The host configuration is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.= h:: =20 struct pxa2xx_spi_controller { @@ -30,7 +30,7 @@ is passed to the driver via a table found in include/linu= x/spi/pxa2xx_spi.h:: }; =20 The "pxa2xx_spi_controller.num_chipselect" field is used to determine the = number of -slave device (chips) attached to this SPI master. +peripheral devices (chips) attached to this SPI host controller. =20 The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP D= MA should be used. This caused the driver to acquire two DMA channels: Rx channel and @@ -40,8 +40,8 @@ See the "PXA2xx Developer Manual" section "DMA Controller= ". For the new platforms the description of the controller and peripheral dev= ices comes from Device Tree or ACPI. =20 -NSSP MASTER SAMPLE ------------------- +NSSP HOST SAMPLE +---------------- Below is a sample configuration using the PXA255 NSSP for a legacy platfor= m:: =20 static struct resource pxa_spi_nssp_resources[] =3D { @@ -57,7 +57,7 @@ Below is a sample configuration using the PXA255 NSSP for= a legacy platform:: }, }; =20 - static struct pxa2xx_spi_controller pxa_nssp_master_info =3D { + static struct pxa2xx_spi_controller pxa_nssp_ctrl_info =3D { .num_chipselect =3D 1, /* Matches the number of chips attached to NSSP */ .enable_dma =3D 1, /* Enables NSSP DMA */ }; @@ -68,7 +68,7 @@ Below is a sample configuration using the PXA255 NSSP for= a legacy platform:: .resource =3D pxa_spi_nssp_resources, .num_resources =3D ARRAY_SIZE(pxa_spi_nssp_resources), .dev =3D { - .platform_data =3D &pxa_nssp_master_info, /* Passed to driver */ + .platform_data =3D &pxa_nssp_ctrl_info, /* Passed to driver */ }, }; =20 @@ -81,17 +81,17 @@ Below is a sample configuration using the PXA255 NSSP f= or a legacy platform:: (void)platform_add_device(devices, ARRAY_SIZE(devices)); } =20 -Declaring Slave Devices ------------------------ -Typically, for a legacy platform, each SPI slave (chip) is defined in the +Declaring peripheral devices +---------------------------- +Typically, for a legacy platform, each SPI peripheral device (chip) is def= ined in the arch/.../mach-*/board-*.c using the "spi_board_info" structure found in "linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional information. =20 -Each slave device attached to the PXA must provide slave specific configur= ation +Each peripheral device (chip) attached to the PXA must provide specific ch= ip configuration information via the structure "pxa2xx_spi_chip" found in -"include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver -will uses the configuration whenever the driver communicates with the slave +"include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi host controller driver +will uses the configuration whenever the driver communicates with the peri= pheral device. All fields are optional. =20 :: @@ -123,7 +123,7 @@ dma_burst_size =3D=3D 0. The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle trailing bytes in the SSP receiver FIFO. The correct value for this field = is dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the spe= cific -slave device. Please note that the PXA2xx SSP 1 does not support trailing= byte +peripheral device. Please note that the PXA2xx SSP 1 does not support trai= ling byte timeouts and must busy-wait any trailing bytes. =20 NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so = the @@ -132,8 +132,8 @@ asserted around the complete message. Use SSPFRM as a G= PIO (through a descriptor to accommodate these chips. =20 =20 -NSSP SLAVE SAMPLE ------------------ +NSSP PERIPHERAL SAMPLE +---------------------- For a legacy platform or in some other cases, the pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data" field. Below is a sample configuration using the PXA255 NSSP. @@ -161,16 +161,16 @@ field. Below is a sample configuration using the PXA2= 55 NSSP. .bus_num =3D 2, /* Framework bus number */ .chip_select =3D 0, /* Framework chip select */ .platform_data =3D NULL; /* No spi_driver specific config */ - .controller_data =3D &cs8415a_chip_info, /* Master chip config */ - .irq =3D STREETRACER_APCI_IRQ, /* Slave device interrupt */ + .controller_data =3D &cs8415a_chip_info, /* Host controller config */ + .irq =3D STREETRACER_APCI_IRQ, /* Peripheral device interrupt */ }, { .modalias =3D "cs8405a", /* Name of spi_driver for this device */ .max_speed_hz =3D 3686400, /* Run SSP as fast a possible */ .bus_num =3D 2, /* Framework bus number */ .chip_select =3D 1, /* Framework chip select */ - .controller_data =3D &cs8405a_chip_info, /* Master chip config */ - .irq =3D STREETRACER_APCI_IRQ, /* Slave device interrupt */ + .controller_data =3D &cs8405a_chip_info, /* Host controller config */ + .irq =3D STREETRACER_APCI_IRQ, /* Peripheral device interrupt */ }, }; =20 --=20 2.43.0.rc1.1.gbec44491f096