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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id i11-20020a5d438b000000b003332ef77db4sm1647628wrq.44.2023.12.07.07.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 07:07:55 -0800 (PST) From: Alexandre Ghiti To: Catalin Marinas , Will Deacon , Thomas Bogendoerfer , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Morton , Ved Shanbhogue , Matt Evans , Dylan Jhong , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH RFC/RFT 4/4] TEMP: riscv: Add debugfs interface to retrieve #sfence.vma Date: Thu, 7 Dec 2023 16:03:48 +0100 Message-Id: <20231207150348.82096-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207150348.82096-1-alexghiti@rivosinc.com> References: <20231207150348.82096-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is useful for testing/benchmarking. Signed-off-by: Alexandre Ghiti --- arch/riscv/include/asm/pgtable.h | 6 ++++-- arch/riscv/include/asm/tlbflush.h | 4 ++++ arch/riscv/kernel/sbi.c | 12 ++++++++++++ arch/riscv/mm/tlbflush.c | 17 +++++++++++++++++ 4 files changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 89aa5650f104..b0855a620cfd 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -550,7 +550,7 @@ static inline int ptep_set_access_flags(struct vm_area_= struct *vma, return false; } =20 -extern u64 nr_sfence_vma_handle_exception; +extern u64 nr_sfence_vma_spurious_read; extern bool tlb_caching_invalid_entries; =20 #define flush_tlb_fix_spurious_read_fault flush_tlb_fix_spurious_read_fault @@ -558,8 +558,10 @@ static inline void flush_tlb_fix_spurious_read_fault(s= truct vm_area_struct *vma, unsigned long address, pte_t *ptep) { - if (tlb_caching_invalid_entries) + if (tlb_caching_invalid_entries) { + __sync_fetch_and_add(&nr_sfence_vma_spurious_read, 1UL); flush_tlb_page(vma, address); + } } =20 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlb= flush.h index a09196f8de68..f419ec9d2207 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -14,14 +14,18 @@ #ifdef CONFIG_MMU extern unsigned long asid_mask; =20 +extern u64 nr_sfence_vma, nr_sfence_vma_all, nr_sfence_vma_all_asid; + static inline void local_flush_tlb_all(void) { + __sync_fetch_and_add(&nr_sfence_vma_all, 1UL); __asm__ __volatile__ ("sfence.vma" : : : "memory"); } =20 /* Flush one page from local TLB */ static inline void local_flush_tlb_page(unsigned long addr) { + __sync_fetch_and_add(&nr_sfence_vma, 1UL); ALT_FLUSH_TLB_PAGE(__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) := "memory")); } #else /* CONFIG_MMU */ diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index c672c8ba9a2a..ac1617759583 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -376,6 +376,8 @@ int sbi_remote_fence_i(const struct cpumask *cpu_mask) } EXPORT_SYMBOL(sbi_remote_fence_i); =20 +extern u64 nr_sfence_vma, nr_sfence_vma_all, nr_sfence_vma_all_asid; + /** * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remo= te * harts for the specified virtual address range. @@ -389,6 +391,11 @@ int sbi_remote_sfence_vma(const struct cpumask *cpu_ma= sk, unsigned long start, unsigned long size) { + if (size =3D=3D (unsigned long)-1) + __sync_fetch_and_add(&nr_sfence_vma_all, 1UL); + else + __sync_fetch_and_add(&nr_sfence_vma, ALIGN(size, PAGE_SIZE) / PAGE_SIZE); + return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, cpu_mask, start, size, 0, 0); } @@ -410,6 +417,11 @@ int sbi_remote_sfence_vma_asid(const struct cpumask *c= pu_mask, unsigned long size, unsigned long asid) { + if (size =3D=3D (unsigned long)-1) + __sync_fetch_and_add(&nr_sfence_vma_all_asid, 1UL); + else + __sync_fetch_and_add(&nr_sfence_vma, ALIGN(size, PAGE_SIZE) / PAGE_SIZE); + return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, cpu_mask, start, size, asid, 0); } diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 77be59aadc73..75a3e2dff16a 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -3,11 +3,16 @@ #include #include #include +#include #include #include =20 +u64 nr_sfence_vma, nr_sfence_vma_all, nr_sfence_vma_all_asid, + nr_sfence_vma_handle_exception, nr_sfence_vma_spurious_read; + static inline void local_flush_tlb_all_asid(unsigned long asid) { + __sync_fetch_and_add(&nr_sfence_vma_all_asid, 1); __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) @@ -17,6 +22,7 @@ static inline void local_flush_tlb_all_asid(unsigned long= asid) static inline void local_flush_tlb_page_asid(unsigned long addr, unsigned long asid) { + __sync_fetch_and_add(&nr_sfence_vma, 1); __asm__ __volatile__ ("sfence.vma %0, %1" : : "r" (addr), "r" (asid) @@ -149,3 +155,14 @@ void flush_pmd_tlb_range(struct vm_area_struct *vma, u= nsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif + +static int debugfs_nr_sfence_vma(void) +{ + debugfs_create_u64("nr_sfence_vma", 0444, NULL, &nr_sfence_vma); + debugfs_create_u64("nr_sfence_vma_all", 0444, NULL, &nr_sfence_vma_all); + debugfs_create_u64("nr_sfence_vma_all_asid", 0444, NULL, &nr_sfence_vma_a= ll_asid); + debugfs_create_u64("nr_sfence_vma_handle_exception", 0444, NULL, &nr_sfen= ce_vma_handle_exception); + debugfs_create_u64("nr_sfence_vma_spurious_read", 0444, NULL, &nr_sfence_= vma_spurious_read); + return 0; +} +device_initcall(debugfs_nr_sfence_vma); --=20 2.39.2