From nobody Fri Dec 19 09:31:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD11FC4167B for ; Thu, 7 Dec 2023 08:20:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378440AbjLGIUG (ORCPT ); Thu, 7 Dec 2023 03:20:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231272AbjLGITo (ORCPT ); Thu, 7 Dec 2023 03:19:44 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2A751721; Thu, 7 Dec 2023 00:19:50 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3B78JdmA126002; Thu, 7 Dec 2023 02:19:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701937179; bh=nyMOFoUOXo46tFBzAl/p0l+r6GPKHW1cw35gPRnnGog=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EVC9PJ03dpyWijfTtY9qV+3XhiO31mGppKrv1sjgYmNIC5FjkNjRR+5WC1cMOc5sd FWyEqxeTdER2FfwSPyn0fUDcPli03RzirHg+PRlQZra1uUr/Atutv7peFOVEY8ZNxV QHQqUpZmyDBEFd05ypQGanQCRqBcL2Fv0QpvZ8C4= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3B78JdqD079735 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Dec 2023 02:19:39 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 7 Dec 2023 02:19:39 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 7 Dec 2023 02:19:39 -0600 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3B78Jd16114488; Thu, 7 Dec 2023 02:19:39 -0600 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.31]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 3B78JcMA024235; Thu, 7 Dec 2023 02:19:39 -0600 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , Tero Kristo , , , MD Danish Anwar Subject: [PATCH 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support Date: Thu, 7 Dec 2023 13:49:16 +0530 Message-ID: <20231207081917.340167-3-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207081917.340167-1-danishanwar@ti.com> References: <20231207081917.340167-1-danishanwar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) port is kept disable and ICSSG1 is enabled in single MAC mode by default. Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 105 ++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index 8c5651d2cf5d..04d1c0602d31 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -34,6 +34,11 @@ aliases { ethernet1 =3D &cpsw_port2; }; =20 + aliases { + ethernet2 =3D &icssg1_emac0; + ethernet3 =3D &icssg1_emac1; + }; + memory@80000000 { bootph-all; device_type =3D "memory"; @@ -229,6 +234,70 @@ transceiver2: can-phy1 { max-bitrate =3D <5000000>; standby-gpios =3D <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible =3D "ti,am642-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_rgmii1_pins_default>; + + sram =3D <&oc_sram>; + ti,prus =3D <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&= tx_pru1_1>; + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg1_mii_g_rt>; + ti,mii-rt =3D <&icssg1_mii_rt>; + ti,iep =3D <&icssg1_iep0>, <&icssg1_iep1>; + + interrupt-parent =3D <&icssg1_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + dmas =3D <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg1_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg1_phy1>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg =3D <1>; + ti,syscon-rgmii-delay =3D <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + status =3D "disabled"; + }; + }; + }; }; =20 &main_pmx0 { @@ -383,6 +452,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 = */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins =3D < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD= 0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD= 1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD= 2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD= 3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_R= XC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX= _CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_= TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_T= D1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_T= D2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_= TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_T= XC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_T= X_CTL */ + >; + }; }; =20 &main_uart0 { @@ -731,3 +824,15 @@ &main_mcan1 { pinctrl-0 =3D <&main_mcan1_pins_default>; phys =3D <&transceiver2>; }; + +&icssg1_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@0 { + reg =3D <0xf>; + tx-internal-delay-ps =3D <250>; + rx-internal-delay-ps =3D <2000>; + }; +}; --=20 2.34.1