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[34.86.254.150]) by smtp.gmail.com with ESMTPSA id g11-20020a0cd7cb000000b0067abdf75926sm187432qvj.14.2023.12.06.10.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 10:47:47 -0800 (PST) From: Paz Zcharya To: Andrzej Hajda , Tvrtko Ursulin Cc: Daniel Vetter , Sean Paul , linux-kernel@vger.kernel.org, Subrata Banik , Nirmoy Das , Paz Zcharya , Drew Davenport , matthew.auld@intel.com, Rodrigo Vivi , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, David Airlie , Marcin Wojtas , Andi Shyti , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Subject: [PATCH] [v2] drm/i915/display: Check GGTT to determine phys_base Date: Wed, 6 Dec 2023 18:46:26 +0000 Message-ID: <20231206184736.3769657-1-pazz@chromium.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There was an assumption that for iGPU there should be a 1:1 mapping of GGTT to physical address pointing to the framebuffer. This assumption is not strictly true effective generation 8 or newer. Fix that by checking GGTT to determine the phys address on gen8+. The following algorithm for phys_base should be valid for all platforms: 1. Find pte 2. if(IS_DGFX(i915) && pte & GEN12_GGTT_PTE_LM) mem =3D i915->mm.regions[INTEL_REGION_LMEM_0] else mem =3D i915->mm.stolen_region 3. phys_base =3D (pte & I915_GTT_PAGE_MASK) - mem->region.start; - On older platforms, stolen_region points to system memory, starting at 0 - on DG2, it uses lmem region which starts at 0 as well - on MTL, stolen_region points to stolen-local which starts at 0x800000 Changes from v1: - Add an if statement for gen7-, where there is a 1:1 mapping Signed-off-by: Paz Zcharya --- .../drm/i915/display/intel_plane_initial.c | 64 +++++++++++-------- 1 file changed, 39 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/g= pu/drm/i915/display/intel_plane_initial.c index a55c09cbd0e4..7d9bb631b93b 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -59,44 +59,58 @@ initial_plane_vma(struct drm_i915_private *i915, return NULL; =20 base =3D round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); - if (IS_DGFX(i915)) { + + if (GRAPHICS_VER(i915) < 8) { + /* + * In gen7-, there is a 1:1 mapping + * between GSM and physical address. + */ + phys_base =3D base; + mem =3D i915->mm.stolen_region; + } else { + /* + * In gen8+, there is no 1:1 mapping between + * GSM and physical address, so we need to + * check GGTT to determine the physical address. + */ gen8_pte_t __iomem *gte =3D to_gt(i915)->ggtt->gsm; gen8_pte_t pte; =20 gte +=3D base / I915_GTT_PAGE_SIZE; - pte =3D ioread64(gte); - if (!(pte & GEN12_GGTT_PTE_LM)) { - drm_err(&i915->drm, - "Initial plane programming missing PTE_LM bit\n"); - return NULL; - } - - phys_base =3D pte & I915_GTT_PAGE_MASK; - mem =3D i915->mm.regions[INTEL_REGION_LMEM_0]; =20 - /* - * We don't currently expect this to ever be placed in the - * stolen portion. - */ - if (phys_base >=3D resource_size(&mem->region)) { - drm_err(&i915->drm, - "Initial plane programming using invalid range, phys_base=3D%pa\n", - &phys_base); - return NULL; + if (IS_DGFX(i915)) { + if (!(pte & GEN12_GGTT_PTE_LM)) { + drm_err(&i915->drm, + "Initial plane programming missing PTE_LM bit\n"); + return NULL; + } + mem =3D i915->mm.regions[INTEL_REGION_LMEM_0]; + } else { + mem =3D i915->mm.stolen_region; } =20 - drm_dbg(&i915->drm, - "Using phys_base=3D%pa, based on initial plane programming\n", - &phys_base); - } else { - phys_base =3D base; - mem =3D i915->mm.stolen_region; + phys_base =3D (pte & I915_GTT_PAGE_MASK) - mem->region.start; } =20 if (!mem) return NULL; =20 + /* + * We don't currently expect this to ever be placed in the + * stolen portion. + */ + if (phys_base >=3D resource_size(&mem->region)) { + drm_err(&i915->drm, + "Initial plane programming using invalid range, phys_base=3D%pa\n", + &phys_base); + return NULL; + } + + drm_dbg(&i915->drm, + "Using phys_base=3D%pa, based on initial plane programming\n", + &phys_base); + size =3D round_up(plane_config->base + plane_config->size, mem->min_page_size); size -=3D base; --=20 2.43.0.472.g3155946c3a-goog