From nobody Sun Nov 10 08:33:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 094B7C4167B for ; Wed, 6 Dec 2023 08:38:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377222AbjLFIiU (ORCPT ); Wed, 6 Dec 2023 03:38:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377191AbjLFIiO (ORCPT ); Wed, 6 Dec 2023 03:38:14 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48CC4C3; Wed, 6 Dec 2023 00:38:20 -0800 (PST) X-UUID: cc2e2580941211ee8051498923ad61e6-20231206 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=73koCofZDqmsIg3RWsQNbfp+mHALtOtkTxc6gTpLsjU=; b=u3hpMb9B6QxC5UjskNllsQoUz1eEy4Ss+/uIrXwarZ3h26wQNZl/YJWJg0KlCW41Fb0HsDI4LgPNc6rN/ZwLTWDwRDy9vd6f5A0EUSW4kVNyHlV+3x6zFFGDeet+oZLR9FhOmn9+NoBa9Q5QgG7fTYxgfSfysl7cGBjtANhCHak=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.34,REQID:13300279-8eb4-4b86-a36f-a92b106e692e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:abefa75,CLOUDID:22c1e060-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: cc2e2580941211ee8051498923ad61e6-20231206 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 796027206; Wed, 06 Dec 2023 16:38:15 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 6 Dec 2023 16:38:13 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 6 Dec 2023 16:38:13 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH 1/2] PCI: mediatek: Allocate MSI address with dmam_alloc_coherent Date: Wed, 6 Dec 2023 16:37:52 +0800 Message-ID: <20231206083753.18186-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231206083753.18186-1-jianjun.wang@mediatek.com> References: <20231206083753.18186-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use 'dmam_alloc_coherent' to allocate the MSI address, instead of using 'virt_to_phys'. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek.c | 29 ++++++++++++++++++-------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 66a8f73296fc..b080f7ca6da0 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -178,6 +178,7 @@ struct mtk_pcie_soc { * @phy: pointer to PHY control block * @slot: port slot * @irq: GIC irq + * @msg_addr: MSI message address * @irq_domain: legacy INTx IRQ domain * @inner_domain: inner IRQ domain * @msi_domain: MSI IRQ domain @@ -198,6 +199,7 @@ struct mtk_pcie_port { struct phy *phy; u32 slot; int irq; + dma_addr_t msg_addr; struct irq_domain *irq_domain; struct irq_domain *inner_domain; struct irq_domain *msi_domain; @@ -394,12 +396,10 @@ static struct pci_ops mtk_pcie_ops_v2 =3D { static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct mtk_pcie_port *port =3D irq_data_get_irq_chip_data(data); - phys_addr_t addr; =20 /* MT2712/MT7622 only support 32-bit MSI addresses */ - addr =3D virt_to_phys(port->base + PCIE_MSI_VECTOR); msg->address_hi =3D 0; - msg->address_lo =3D lower_32_bits(addr); + msg->address_lo =3D lower_32_bits(port->msg_addr); =20 msg->data =3D data->hwirq; =20 @@ -515,18 +515,26 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_p= cie_port *port) return 0; } =20 -static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) +static int mtk_pcie_enable_msi(struct mtk_pcie_port *port) { u32 val; - phys_addr_t msg_addr; + void *msi_vaddr; =20 - msg_addr =3D virt_to_phys(port->base + PCIE_MSI_VECTOR); - val =3D lower_32_bits(msg_addr); + msi_vaddr =3D dmam_alloc_coherent(port->pcie->dev, sizeof(dma_addr_t), &p= ort->msg_addr, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(port->pcie->dev, "failed to alloc and map MSI data\n"); + return -ENOMEM; + } + + val =3D lower_32_bits(port->msg_addr); writel(val, port->base + PCIE_IMSI_ADDR); =20 val =3D readl(port->base + PCIE_INT_MASK); val &=3D ~MSI_MASK; writel(val, port->base + PCIE_INT_MASK); + + return 0; } =20 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) @@ -732,8 +740,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_po= rt *port) val &=3D ~INTX_MASK; writel(val, port->base + PCIE_INT_MASK); =20 - if (IS_ENABLED(CONFIG_PCI_MSI)) - mtk_pcie_enable_msi(port); + if (IS_ENABLED(CONFIG_PCI_MSI)) { + err =3D mtk_pcie_enable_msi(port); + if (err) + return err; + } =20 /* Set AHB to PCIe translation windows */ val =3D lower_32_bits(mem->start) | --=20 2.18.0