From nobody Mon Feb 9 13:00:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DCF1C4167B for ; Tue, 5 Dec 2023 08:05:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234922AbjLEIF0 (ORCPT ); Tue, 5 Dec 2023 03:05:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376355AbjLEIE7 (ORCPT ); Tue, 5 Dec 2023 03:04:59 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE48719F; Tue, 5 Dec 2023 00:05:04 -0800 (PST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B4NxDqJ021827; Tue, 5 Dec 2023 00:04:54 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=aWngtRDxPwzlvoiaiZGqPUHzdIBT5rG+oxF0CqsGxLE=; b=TpbewK1YrFCAA81Fr1IwuDUjqX/iKS6P6MWrcwciMtS2UVOmpCiri0rYx7Rz0IPmvwAZ 2xGfW6IMFezoqemlegvEwPsEQVNLe2M/YxfJmBr6NyXVDioWGUo2iMEGIyPgckj0vqMK UN+8YyofTM3Nb+3704juQ83kubKklMe73r5Kv/ZmnVhxz4bO6Gzf6dvndNwcUZGFUY2z OJ3rX9WXk7Fvfb6Ip5c+BAbDOJaG7nXPRDl8bZOe+j4Jgkk0WABo4Qs3w0rT2ofFZylk uia2JLUUswlWZkIvRyKSGVr9UIAEqYJGWlGrOIhaEQKrInxCOt20py8s3Uwzfndw9I2A yg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3usrx3h83p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 05 Dec 2023 00:04:53 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 5 Dec 2023 00:04:52 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 5 Dec 2023 00:04:52 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id BD2E03F70A9; Tue, 5 Dec 2023 00:04:48 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , , Subject: [net v4 PATCH 3/5] octeontx2-af: Fix mcs stats register address Date: Tue, 5 Dec 2023 13:34:32 +0530 Message-ID: <20231205080434.27604-4-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231205080434.27604-1-gakula@marvell.com> References: <20231205080434.27604-1-gakula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: HA4Ffe0DlSZOAxNc1k_3j8p1m5dVr0Sz X-Proofpoint-ORIG-GUID: HA4Ffe0DlSZOAxNc1k_3j8p1m5dVr0Sz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_03,2023-12-04_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds the miss mcs stats register for mcs supported platforms. Fixes: 9312150af8da ("octeontx2-af: cn10k: mcs: Support for stats collectio= n") Signed-off-by: Geetha sowjanya Reviewed-by: Wojciech Drewek --- .../net/ethernet/marvell/octeontx2/af/mcs.c | 4 +-- .../ethernet/marvell/octeontx2/af/mcs_reg.h | 31 ++++++++++++++++--- 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/= ethernet/marvell/octeontx2/af/mcs.c index bd87507cf8ea..c1775bd01c2b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c @@ -117,7 +117,7 @@ void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_= secy_stats *stats, int id reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(id); stats->pkt_tagged_ctl_cnt =3D mcs_reg_read(mcs, reg); =20 - reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(id); + reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(id); stats->pkt_untaged_cnt =3D mcs_reg_read(mcs, reg); =20 reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(id); @@ -215,7 +215,7 @@ void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_st= ats *stats, reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(id); stats->pkt_notvalid_cnt =3D mcs_reg_read(mcs, reg); =20 - reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(id); + reg =3D MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(id); stats->pkt_unchecked_cnt =3D mcs_reg_read(mcs, reg); =20 if (mcs->hw->mcs_blks > 1) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h b/drivers/= net/ethernet/marvell/octeontx2/af/mcs_reg.h index f3ab01fc363c..f4c6de89002c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h @@ -810,14 +810,37 @@ offset =3D 0x9d8ull; \ offset; }) =20 +#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(a) ({ \ + u64 offset; \ + \ + offset =3D 0xee80ull; \ + if (mcs->hw->mcs_blks > 1) \ + offset =3D 0xe818ull; \ + offset +=3D (a) * 0x8ull; \ + offset; }) + +#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) ({ \ + u64 offset; \ + \ + offset =3D 0xa680ull; \ + if (mcs->hw->mcs_blks > 1) \ + offset =3D 0xd018ull; \ + offset +=3D (a) * 0x8ull; \ + offset; }) + +#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) ({ \ + u64 offset; \ + \ + offset =3D 0xf680ull; \ + if (mcs->hw->mcs_blks > 1) \ + offset =3D 0xe018ull; \ + offset +=3D (a) * 0x8ull; \ + offset; }) + #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(a) (0xe680ull + (a) * 0= x8ull) #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(a) (0xde80ull + (a) * 0x= 8ull) -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(a) (0xa680ull + (= a) * 0x8ull) #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(a) (0xd218 + (a) * 0x8ull) -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) (0xd018ull + (a) * 0x= 8ull) -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(a) (0xee80ull + (a) *= 0x8ull) #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(a) (0xb680ull + (a) * 0x8ull) -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) (0xf680ull + (a) *= 0x8ull) #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(a) (0x12680ull + (a) * 0x8u= ll) #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(a) (0x15680ull + (a= ) * 0x8ull) #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(a) (0x13680ull + (a) * 0x8= ull) --=20 2.25.1