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charset="utf-8" 'pf' and 'lut' is just difference name in difference chips, but basic it is a MMIO base address plus an offset. Rename it to avoid duplicate pf_* and lut_* in driver. Reviewed-by: Manivannan Sadhasivam Acked-by: Roy Zang Signed-off-by: Frank Li --- Notes: pf_lut is better than pf_* or lut* because some chip use 'pf', some chip use 'lut'. =20 Change from v5 to v6 move to previous patch -> - .ops =3D &ls_pcie_host_ops; > + .ops =3D &ls_pcie_host_ops, =20 Change from v4 to v5 - rename layerscape-ep code also change from v1 to v4 - new patch at v3 .../pci/controller/dwc/pci-layerscape-ep.c | 16 ++++----- drivers/pci/controller/dwc/pci-layerscape.c | 34 +++++++++---------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/c= ontroller/dwc/pci-layerscape-ep.c index 3d3c50ef4b6ff..2ca339f938a86 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -49,7 +49,7 @@ struct ls_pcie_ep { bool big_endian; }; =20 -static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) { struct dw_pcie *pci =3D pcie->pci; =20 @@ -59,7 +59,7 @@ static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offs= et) return ioread32(pci->dbi_base + offset); } =20 -static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) +static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32= value) { struct dw_pcie *pci =3D pcie->pci; =20 @@ -76,8 +76,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) u32 val, cfg; u8 offset; =20 - val =3D ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); - ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); + val =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); =20 if (!val) return IRQ_NONE; @@ -96,9 +96,9 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); dw_pcie_dbi_ro_wr_dis(pci); =20 - cfg =3D ls_lut_readl(pcie, PEX_PF0_CONFIG); + cfg =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG); cfg |=3D PEX_PF0_CFG_READY; - ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg); dw_pcie_ep_linkup(&pci->ep); =20 dev_dbg(pci->dev, "Link up\n"); @@ -130,10 +130,10 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_e= p *pcie, } =20 /* Enable interrupts */ - val =3D ls_lut_readl(pcie, PEX_PF0_PME_MES_IER); + val =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER); val |=3D PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE | PEX_PF0_PME_MES_IER_LUDIE; - ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); =20 return 0; } diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/cont= roller/dwc/pci-layerscape.c index 711563777aeba..f3dfb70066fb7 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -44,7 +44,7 @@ #define PCIE_IATU_NUM 6 =20 struct ls_pcie_drvdata { - const u32 pf_off; + const u32 pf_lut_off; const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); bool scfg_support; @@ -54,13 +54,13 @@ struct ls_pcie_drvdata { struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; - void __iomem *pf_base; + void __iomem *pf_lut_base; struct regmap *scfg; int index; bool big_endian; }; =20 -#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) +#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) =20 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -101,20 +101,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie= *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } =20 -static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off) { if (pcie->big_endian) - return ioread32be(pcie->pf_base + off); + return ioread32be(pcie->pf_lut_base + off); =20 - return ioread32(pcie->pf_base + off); + return ioread32(pcie->pf_lut_base + off); } =20 -static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) { if (pcie->big_endian) - iowrite32be(val, pcie->pf_base + off); + iowrite32be(val, pcie->pf_lut_base + off); else - iowrite32(val, pcie->pf_base + off); + iowrite32(val, pcie->pf_lut_base + off); } =20 static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) @@ -124,11 +124,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_r= p *pp) u32 val; int ret; =20 - val =3D ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val =3D ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |=3D PF_MCR_PTOMR; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); =20 - ret =3D readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret =3D readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_PTOMR), PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); @@ -147,15 +147,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link * to exit L2 state. */ - val =3D ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val =3D ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |=3D PF_MCR_EXL2S; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); =20 /* * L2 exit timeout of 10ms is not defined in the specifications, * it was chosen based on empirical observations. */ - ret =3D readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret =3D readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_EXL2S), 1000, 10000); @@ -242,7 +242,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata =3D= { }; =20 static const struct ls_pcie_drvdata layerscape_drvdata =3D { - .pf_off =3D 0xc0000, + .pf_lut_off =3D 0xc0000, .pm_support =3D true, .ops =3D &ls_pcie_host_ops, .exit_from_l2 =3D ls_pcie_exit_from_l2, @@ -291,7 +291,7 @@ static int ls_pcie_probe(struct platform_device *pdev) =20 pcie->big_endian =3D of_property_read_bool(dev->of_node, "big-endian"); =20 - pcie->pf_base =3D pci->dbi_base + pcie->drvdata->pf_off; + pcie->pf_lut_base =3D pci->dbi_base + pcie->drvdata->pf_lut_off; =20 if (pcie->drvdata->scfg_support) { pcie->scfg =3D syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-s= cfg"); --=20 2.34.1